Unpredictable design

Thu Feb 18, 2010 12:55 am   

Hello !

I have a very big problem. I created a simple procesor and on simulation i
works fine, on step mode it works fine but when it is running on full spee
of clock it got crazy... It should execute instruction i orde
0.1.2.3.4.5 (Program Counter values and PC is connected to leds) and i
executes sometimes 0.1.3.5 some times 0.1.2.3.4.5.6.7.8.9 or 0.1.2.6.3.4 o
0.1 or sometimes it is as it should. Sometimes it stops suddenly executin
or executing too much. It is written in VHDL on Spartan 3A. It is too bi
to show it here but maybe some experts will be able to tell me what i
going on... I have constraints like this in UCF file :

NET "Clock" LOC = C10;
NET "Clock" IOSTANDARD = LVCMOS33;
NET "Clock" PERIOD = 62.5ns HIGH 50%;
NET "Reset" LOC = H4;
NET "Reset" IOSTANDARD = LVCMOS33;
NET "TX" LOC = B3;
NET "TX" IOSTANDARD = LVCMOS33;
NET "RX" LOC = A3;
NET "RX" IOSTANDARD = LVCMOS33;

are there any other constraint useful for me ? Can it be constraint fault
Or it must be design problem ? Or something else ? 16Mhz clock i
connected to FPGA. It works OK using step by step mode but on full spee
it's stragne bevahior... I really need help, I trying to solve it for thre
days and nothing...

Thank you all for any answers...

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Thu Feb 18, 2010 1:04 am   

On 2/17/2010 11:55 PM, de4 wrote:

What is 'step mode' exactly? Your clock is relatively slow. So, your
problem is probably something to do with clock skew. Is your clock on a
GBUF? Does your clock connect to anything other than a dedicated clock
input of the FPGAs innards?

HTH Syms.

Thu Feb 18, 2010 3:32 am   

On Feb 17, 3:55 pm, "de4" <de4_at_n_o_s_p_a_m.poczta.onet.pl> wrote:

You don't mention if the design passes P&R with no timing errors.
Simply specifying constraints
doesn't mean they are actually met.

John Providenza

Thu Feb 18, 2010 9:04 am   

I'm bigginner so I was trying to verify if my work actually works in FPGA.
So as clock of whole system I used FSM controled by push button. When
push the button it gave one clock cycle and because that processor gone t
next state - this is what I meant saying 'step mode'. I have writte
software that reads all registers and memory and sending do computer. An
there everything looks ok...

Sorry but I don;t know what is GBUF ? I will find it out...
My clock isn't comnected to anything else then to FPGA ( I have Avne
Sparatan 3A board)

And about constraints in Map messages I have only : (only infos)

MapLib:562 - No environment variables are currently set.

MapLib:159 - Net Timing constraints on signal Clock are pushed forwar
through input buffer.

LIT:244 - All of the single ended outputs in this design are using sle
rate limited output drivers. The delay on speed critical single ende
outputs can be dramatically reduced by designating them as fast outputs.

It doesn't tell me a lot :(

Timing messages

Timing:2752 - To get complete path coverage, use the unconstrained path
option. All paths that are not constrained will be reported in th
unconstrained paths section(s) of the report.

Timing:3339 - The clock-to-out numbers in this timing report are based on
50 Ohm transmission line loading model. For the details of this model, an
for more information on accounting for different loading conditions, pleas
see the device datasheet.

And in detailed Post-PAR Static Timing Report is written
All constraints were met.

What Can I check more ?

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Thu Feb 18, 2010 11:42 am   

On Wed, 17 Feb 2010 17:55:07 -0600, "de4" <de4_at_n_o_s_p_a_m.poczta.onet.pl>
wrote:


16MHz is slow enough that problems meeting timing are unlikely.

Is the processor accessing any memory external to the FPGA, or just thu internal
BRAMs? External memory is a likely source of timing problems.

Check for any inputs to the processor that aren't themselves clocked by the same
clock, and eliminate them (by reclocking them from the CPU clock.

- Brian

Thu Feb 18, 2010 1:12 pm   

Thank you for response...

Processor don't accessing external memory only BlockRAM based RAM.
I have one input in my system that is a clock connected to global clock.
this input is (clock signal) connected to processor, ram and I/O ( uses TX
and RX line to communicate with processor from outside). Processor is
connected with Clock, Reset and RAM signals. RAM is connected with Clock,
Processor and to I/O unit (dual port). To I/O unit is connected clock,
Reset and signal from ram and TX,RX lines.

I writing because it is strage behavior I even could say that it is
randomly...
If something would be wrongly design (I mean some fsm in control unit)
program would be executed badly but always in the same way... In my case
some times is
PC values are 0, 1 ,2 ,4, 5 some times it is 0, 1 and stops.
16 Mhz is not too much...

Best regards,
Maciek




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Thu Feb 18, 2010 1:37 pm   

On 2/18/2010 12:12 PM, de4 wrote:

Can you use chipscope to look at the signals which control the program
counter, and the PC's value?
Do you get any warnings from P&R something like "Warning: Signal clock
connects to non-clock resource"?

Look in all the report files for any warnings to do with your clock signal.

Does your reset get released synchronously to the clock?

HTH, Syms.

Thu Feb 18, 2010 2:11 pm   

Chipscope is beyond my possibilities... I program FPGA using Avnet Program
and I don't have Platform Cable... In PAR I don't have any warnings a
all...
I will search them but I didn't see any warnings.

Sorry but "Does your reset get released synchronously to the clock?"
I don;t understand this - I have some Dff like this :

entity D_FF is
port( D, Clock, Reset : in STD_LOGIC;
Q, notQ : out STD_LOGIC);
end D_FF;

architecture CPU of D_FF is
signal Qout : STD_LOGIC;
begin

PROCESS(D, Clock, Reset)
BEGIN
IF Reset = '1' THEN -- Don’t wait for clock
Q <= '0';
notQ <= '1';
ELSIF (Clock'event) AND (Clock='1') THEN -- Positive Edge
Q <= D;
notQ <= not D;
END IF;
END PROCESS;

end CPU;


and this reset is connected to button on a board...
So I think rather not...

Thank you for response...

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Thu Feb 18, 2010 4:55 pm   

On 2/18/2010 1:11 PM, de4 wrote:

So, it probably isn't the problem, but why is 'D' in your sensitivity list?

You should build a debounce circuit for the reset button that is
synchronous to your clock.

http://en.wikipedia.org/wiki/Switch#Contact_bounce

HTH., Syms.

Thu Feb 18, 2010 4:59 pm   

Also

http://www.xilinx.com/support/documentation/white_papers/wp272.pdf

Thu Feb 18, 2010 5:51 pm   

Okey I will try it, I only wondering if those papers telling abou
problems with debouncing and does it refers also to capacity switches ?

About case why D in on sensitivity list - I must tell I don't now, I wil
remove it from there...

Thank you for intresting in my stupid case,
I will try trick with debounce and will see...

Once again thank you for ideas :)

Best Regards,
Maciek

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Thu Feb 18, 2010 6:49 pm   

On Wed, 17 Feb 2010 17:55:07 -0600, "de4" <de4_at_n_o_s_p_a_m.poczta.onet.pl> wrote:


Have you tried running at a lower clock rate?
This would seem a simple way of determining if it is a per-cycle overall path delay type thing or a
setup/hold, race condition etc. due to internal propagation times.

Fri Feb 19, 2010 2:38 pm   

Just to be devil's advocate, it still seems as if timing/skew is not
met, although you have indicated otherwise (1 - PERIOD=62.5ns, 2 - no
timing errors). Can you configure the STA tool to list the longest
routes (even though they are passing), just to get an idea that it is
being measured for the 16 MHz? In other words, prove that design is
being timed to 16 MHz.

Fri Feb 19, 2010 10:59 pm   

I read those documents and I stared to looking at does resets.
I've changed all D flip flops. Now they are reset synch. because asynch
reset is a bad practice. In document wp272 I read that I don't need globa
reset at all. But I notice two things.

1. When I reconfigure FPGA and don't touch anything on a board proceso
executes program wrongly. When executing is finished and I resert proceso
it executes program in good way.

2. When I reconfigure FPGA and I will hold reset button until downloa
process will be finished and I will realase button it executes good also.

Where can be a problem ? Should I use some GSR net ? I heard it is not goo
solution also... If I should what is best practise ? Or maybe some settin
in CoreGen (ram) are bad - I don't use any EN oraz RST pins in m
design...

Thank you for any response.

Regards,
Maciek





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Sat Feb 20, 2010 6:25 pm   

On 2/19/2010 9:59 PM, de4 wrote:

It sounds as though some state machine in your design is set to the
proper initial conditions when the FPGA is loaded. You should be able to
find this with simulation.
HTH., Syms.