Unconstrained array: How would this component be described

Mon Jun 14, 2010 11:57 am   

Hi all!
I am not a syntax expert, I tend to use as simple and direct methods
as possible to describe what I want, but now I have the task of
recreating a package with components used in a legacy design where
parts of the original code was lost. In it there are several
references to a bus delay module, instantiated with different data
widths but with no generic to control said width. I suppose this can
be done by using the "length" attribute of the connected signals, but
there is a generic to control what I think is the reset value that is
giving me greif. How would you modify the code below so that it would
at least compile?

In some instances, the module is instantiated with a generic value for
"Init" and all is fine, but in some instances (as below), the generic
is omitted, giving the error: "(vcom-1031) Formal generic "init" has
OPEN or no actual associated with it.". I can not use "(OTHERS =>
'0')" for an unconstrainer array.

Code example:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY test IS
PORT (
CLK : IN std_logic; -- Clock
RST : IN std_logic; -- Reset
D : IN std_logic_vector; -- Data in
Q : OUT std_logic_vector -- Data out
);
END ENTITY test;

ARCHITECTURE rtl OF test IS

COMPONENT bus_delay IS
GENERIC (
Delay : natural := 1; -- Number of clock cycles
delay
Init : std_logic_vector -- Reset value
);
PORT (
CLK : IN std_logic; -- Clock
RST : IN std_logic; -- Reset
D : IN std_logic_vector; -- Data in
Q : OUT std_logic_vector -- Data out
);
END COMPONENT bus_delay;

BEGIN -- rtl

i_bus_delay : bus_delay
PORT MAP(
CLK => CLK,
RST => RST,
D => D,
Q => Q
);
END COMPONENT bus_delay;

END rtl;

Thanks!
/Lars

P.S. Remove the obvious from the email address if you want to email me
directly. D.S.

Mon Jun 14, 2010 11:57 am   

On 14/06/2010 09:57, Lars wrote:
<snip>

You can try this
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY test IS
PORT (
CLK : IN std_logic; -- Clock
RST : IN std_logic; -- Reset
D : IN std_logic_vector; -- Data in
Q : OUT std_logic_vector -- Data out
);
END ENTITY test;

ARCHITECTURE rtl OF test IS

COMPONENT bus_delay IS
GENERIC (
Delay : natural := 1; -- Number of clock cycles delay
Init : std_logic_vector -- Reset value
);
PORT (
CLK : IN std_logic; -- Clock
RST : IN std_logic; -- Reset
D : IN std_logic_vector; -- Data in
Q : OUT std_logic_vector -- Data out
);
END COMPONENT bus_delay;

BEGIN -- rtl

i_bus_delay : bus_delay
generic map (init => (D'RANGE => '0')) -- *********************
PORT MAP(
CLK => CLK,
RST => RST,
D => D,
Q => Q
);
-- END COMPONENT bus_delay; -- I deleted this line

END rtl;

--
Alan Fitch
Senior Consultant

Doulos – Developing Design Know-how
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Mon Jun 14, 2010 2:07 pm   

On 14/06/2010 13:55, Lars wrote:

Hi Lars,
just to be clear - when you say "the component declaration that I
included in my example is missing", are you saying that the code you
have uses direct instantiation (there are no component declarations)?

regards
Alan

--
Alan Fitch
Senior Consultant

Doulos – Developing Design Know-how
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Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: + 44 (0)1425 471223 Email: alan.fitch_at_doulos.com
Fax: +44 (0)1425 471573 http://www.doulos.com

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Mon Jun 14, 2010 3:55 pm   

Hi Alan!
Thanks for the answer. That would work fine, but I was hooping to
avoid altering the existing code and instead create the component to
match. I made the short module above to illustrate the problem, but in
the legacy code, the component declaration that I included in my
example is missing, and the only trace of the generics are that in
some instances they are present in the instantiation and in some
instances they are not. When they are present, all works fine. The
problem is when they are not...

Thanks!
/Lars

Mon Jun 14, 2010 4:35 pm   

On 14/06/2010 13:55, Lars wrote:

OK, plan B - write your own bus delay module called bus_delay, but with
the original generics modified, as follows

entity bus_delay IS
GENERIC (
Delay : natural; -- Number of clock cycles delay
Init : natural -- Reset value
);
PORT (
CLK : IN std_logic; -- Clock
RST : IN std_logic; -- Reset
D : IN std_logic_vector; -- Data in
Q : OUT std_logic_vector -- Data out
);
END entity bus_delay;

architecture rtl of bus_delay is

begin

process(clk,rst)
begin
if rst = '1' then
q <= std_logic_vector(to_unsigned(init, d'length));
elsif rising_edge(clk) then
q <= d;
end if;
end process;

end architecture RTL;

The component declaration can have a default value of 0.
You'll be limited to 32 bits.

Anywhere where the generics are used, it will just carry on working.

Anywhere where the generics *are* used, you'll have to modify the
generic map

init => to_integer(unsigned(initval))

Assuming that most of the instances use the default generic, that should
minimize the number of edits to your code.

Unfortunately, I can't think of an easy way round the problem otherwise
- perhaps someone else has some ideas,

regards
Alan


--
Alan Fitch
Senior Consultant

Doulos – Developing Design Know-how
VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project
Services

Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: + 44 (0)1425 471223 Email: alan.fitch_at_doulos.com
Fax: +44 (0)1425 471573 http://www.doulos.com

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Mon Jun 14, 2010 8:52 pm   

In order to compile with no generic map on the component
instantiation, the component generic declaration must have a default
value (or maybe the entity declaration?). How the architecture handles
that generic is up to whoever wrote it. It does not necessarily have
to match the size of the data. The architecture for bus_delay could
check to see if it matches, and if not, apply some default rule for
initialization. I would personally set it up such that the default
generic value was (0 => '0'), which is an slv of length 1 with the
only bit being '0'. Then the architecture could check to see if
init'length = 1, and if so, apply the single bit to every bit in the
data bus. Otherwise it could make sure it matched the length of the
data, and just use it as is. Anything else, and assert a failure or
default to something (like (others=>'0').

Andy

Tue Jun 15, 2010 2:33 am   

On Jun 14, 4:57 am, Lars <noreply.lar...@gmail.com> wrote:

Which code was actually lost? The 'bus_delay' module or the code that
instantiates the 'bus_delay' module?


From this, I assume that what was lost was the code for 'bus_delay'
module since if you have the code for 'bus_delay' then to figure out
what the generic 'init' is supposed to do, you would simply look at
the code.


No, but you can use any vector as the default in order to get it to
compile

entity bus_delay IS
GENERIC (
Delay : natural := 1; -- Number of clock cycles delay
Init : std_logic_vector := "0" -- Reset value
);
....

The 'problem' is that just because it compiles doesn't mean that it's
correct. You need to know how 'Init' is being used and try to figure
out what the designer's intention was when they accepted the default
value by not assigning it when instantiating the entity. In order to
figure this out, you need to look at how 'Init' is being used in
'bus_delay' and take a guess...but then if the lost code is
'bus_delay' and you're recreating it, then you need to look at how
*you* are using 'Init'.

If there are any assignements like "q <= init;" then the designer made
the assumption that 'q' and 'init' must be the same size vector. If
you peruse the instantiations of 'bus_delay', you will likely find
that each case where 'init' was not overridden on the generic map,
that the size of whatever signal is assigned to the 'q' port is always
the same (for example, maybe 'q' is always assigned to 8 bit
vectors). Now you know that 'init' must be an 8 bit vector, further
sleuthing might uncover what the value should be, but likely it
won't...but the wild guess is probably "00000000".

Happy hunting and good luck.

Kevin Jennings

Tue Jun 15, 2010 9:38 am   

On 14/06/2010 18:52, Andy wrote:

Hi Andy,
I tried that out (default of "0" on the component, no default on the
entity). It simulated fine, but it failed in synthesis (I tried it in
Altera Quartus).

That's why I suggested in the end that changing to an integer generic
might be the only option.

I'll have to try it again with defaults of "0" on both component and
entity, but I suspect it will still cause problems in synthesis,

regards
Alan


--
Alan Fitch
Senior Consultant

Doulos – Developing Design Know-how
VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project
Services

Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: + 44 (0)1425 471223 Email: alan.fitch_at_doulos.com
Fax: +44 (0)1425 471573 http://www.doulos.com

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This message may contain personal views which are not the views of
Doulos, unless specifically stated.

Tue Jun 15, 2010 12:46 pm   

Alan, Andy, Kevin, thanks for the input! I have been AFK but here are
some comments:

The component is missing and all I have is direct instantiations.

The component is instantiated in different places with different port
widths so I can not deduce the generic from that.

In one instance, Init would be set to "00000000", in another it would
be set to "0000000000000000". In these cases the signals connected to
D and Q have sizes to match (std_logic_vector(7 DOWNTO 0) and
std_logic_vector(15 DOWNTO 0) respectively) and all is fine. But in
some cases, the module is instantiated without a generic map, or with
an incomplete generic map lacking Init. I though that there might be a
clever way to specify the generic in the entity of the component so
that it would adapt to D and Q and still get a default value (likely
"(OTHERS => '0')" but that can not be set on an unconstrained array),
but from what I understand by your comments that might not be the
case.

I have a sneaking suspicion that what I have are code fragments from
different versions of the design. As Kevin pointed out, I have to
understand the designers intent with the signal and that might not be
so easy. So I will dig deeper and try to understand more and maybe in
the end I will get it. As a last resort I will modify the code.

Thanks once again for your efforts, it is invaluable to have a forum
like this!

Cheers!
/Lars

Tue Jun 15, 2010 4:50 pm   

Do you mean the code you have uses direct ENTITY instantiations, or
just that you have code that does the component instantiations, but
don't have the component declarations? If you have code that uses
entity instantiations, you don't need component declarations at all.

Do you have the entity/architecture code for bus_delay?

If so, what does it do with the init generic?

If not, you'll just have to make an educated guess. KJ has given you
some excellent tips on gleaning the original intent of the generic. It
could also be that no init meant no reset. In that case, a default
value like "-" might be best (or maybe a null vector?), and since you
are the one that will re-write the entity/architecture, you can figure
out what to do if the generic is "-", "", or if it has been changed to
"0", "1" or some bit string that matches the data'length.

Andy