Fri May 06, 2016 4:47 pm
We were using ATLYS FPGA board and want to implement Uart. Here is the link to the VHDL code -
In this code 8 bits of data is sent serially through the UART port into the FPGA at a time and this data is at the same time emitted out of the FPGA. The data sending part is done by the C code that can be found here -
This c code can be used to read the data from a text file, which is serially sent into the FPGA which emits it back and stores it into another text file.
What I want to do is to store this data into a variable. Can anyone kindly help?
Fri May 06, 2016 10:45 pm
On 5/6/2016 10:47 AM, soumik.kanad_at_gmail.com wrote:
I believe you are trying to store the bytes received by the UART into a
The first problem is the use of IEEE.STD_LOGIC_UNSIGNED. This is a
deprecated library which is *not* an IEEE standard or even a standard at
all and is defined differently on different systems. So you can get
inconsistent results across different systems. So get rid of it and use
numeric_std which *is* an IEEE standard producing identical results on
all systems. You will need to declare your arithmetic types as unsigned.
Or... if you are working with VHDL 2008, you should have available a
package called numeric_std_unsigned which again *is* an IEEE standard
and will do what std_logic_unsigned intends to do, but in a standard way.
Looking at the code I see an output flag called "rx_enable" which seems
to be the data available indicator. It is set by the rx input at the
time of the stop bit so will not go high if a framing error is detected.
This bit goes high when the UART receiver enters the idle state and is
reset on the next clock. So you should be able to use the rx_enable
signal to enable a register to capture the data in the rx_data register.