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Transmission Gate FF

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Ricky C
Guest

Wed May 06, 2020 3:45 am   



The TI SN74HCS72 has a diagram showing the internal transmission gate structure and I must be misinterpreting how it works. The device is negative edge triggered but the logic seems to me to be positive edge sensitive.

For negative edge triggering, the first set of transmission gates should be accepting input through the gates when the clock is high. The second FF is set to hold it's present value. When the clock drops the first FF holds it's value while the second FF opens and flow that value to the output.

Here's the diagram. Tell me this isn't positive edge triggered! Maybe the reused a diagram from some other document since most FFs are positive edge triggered.

http://www.ti.com/data-sheets/diagram.tsp?genericPartNumber=SN74HCS72&diagramId=SCLS801

Full data sheet here.

http://www.ti.com/lit/ds/symlink/sn74hcs72.pdf?ts=1588731244057

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Rick C.

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Mark
Guest

Wed May 06, 2020 5:45 am   



On Tuesday, May 5, 2020 at 7:42:31 PM UTC-7, Ricky C wrote:
Quote:
The TI SN74HCS72 has a diagram showing the internal transmission gate structure and I must be misinterpreting how it works. The device is negative edge triggered but the logic seems to me to be positive edge sensitive.

For negative edge triggering, the first set of transmission gates should be accepting input through the gates when the clock is high. The second FF is set to hold it's present value. When the clock drops the first FF holds it's value while the second FF opens and flow that value to the output.

Here's the diagram. Tell me this isn't positive edge triggered! Maybe the reused a diagram from some other document since most FFs are positive edge triggered.

http://www.ti.com/data-sheets/diagram.tsp?genericPartNumber=SN74HCS72&diagramId=SCLS801

Full data sheet here.

http://www.ti.com/lit/ds/symlink/sn74hcs72.pdf?ts=1588731244057

--

Rick C.

- Get 1,000 miles of free Supercharging
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Looks right to me: External CLK/ is tied to internal C/. C/ goes to the gate of the D input NFET; C goes to the PFET. So, CLK/ high enables the CMOS switch.

-Mark

Johann Klammer
Guest

Wed May 06, 2020 5:45 am   



On 05/06/2020 04:42 AM, Ricky C wrote:
Quote:
The TI SN74HCS72 has a diagram showing the internal transmission gate structure and I must be misinterpreting how it works. The device is negative edge triggered but the logic seems to me to be positive edge sensitive.

For negative edge triggering, the first set of transmission gates should be accepting input through the gates when the clock is high. The second FF is set to hold it's present value. When the clock drops the first FF holds it's value while the second FF opens and flow that value to the output.

Here's the diagram. Tell me this isn't positive edge triggered! Maybe the reused a diagram from some other document since most FFs are positive edge triggered.

http://www.ti.com/data-sheets/diagram.tsp?genericPartNumber=SN74HCS72&diagramId=SCLS801

Full data sheet here.

http://www.ti.com/lit/ds/symlink/sn74hcs72.pdf?ts=1588731244057


/C is the same as input clock

(1)the gates at the input and also the feedback loop at the output
are active if it's high.

(2)When it goes low, the input gets disconnected and the first stage
fb loop runs. this gets also routed to the output at the same time.
(this is the negative edge trigger)

(1)When it goes back up, the slave loop at the output will hold the value.

Ricky C
Guest

Wed May 06, 2020 7:45 am   



On Wednesday, May 6, 2020 at 12:13:44 AM UTC-4, Johann Klammer wrote:
Quote:
On 05/06/2020 04:42 AM, Ricky C wrote:
The TI SN74HCS72 has a diagram showing the internal transmission gate structure and I must be misinterpreting how it works. The device is negative edge triggered but the logic seems to me to be positive edge sensitive.

For negative edge triggering, the first set of transmission gates should be accepting input through the gates when the clock is high. The second FF is set to hold it's present value. When the clock drops the first FF holds it's value while the second FF opens and flow that value to the output.

Here's the diagram. Tell me this isn't positive edge triggered! Maybe the reused a diagram from some other document since most FFs are positive edge triggered.

http://www.ti.com/data-sheets/diagram.tsp?genericPartNumber=SN74HCS72&diagramId=SCLS801

Full data sheet here.

http://www.ti.com/lit/ds/symlink/sn74hcs72.pdf?ts=1588731244057


/C is the same as input clock

(1)the gates at the input and also the feedback loop at the output
are active if it's high.

(2)When it goes low, the input gets disconnected and the first stage
fb loop runs. this gets also routed to the output at the same time.
(this is the negative edge trigger)

(1)When it goes back up, the slave loop at the output will hold the value..


Ok, I was missing the fact that the /C was the same as the external clock. Even when it is negative edge, to me it's just the clock rather than clock not.

Thanks.

--

Rick C.

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elektroda.net NewsGroups Forum Index - Electronics Design - Transmission Gate FF

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