To get higher clock frequencies at output using propagation

Hi,

I'm implementing this project where I've to generate higher output clk
frequencies using DCM module. I have used a counter for delay
generator, for propagation delays(Pls suggest if there is any other
method). I have also instantiated the DCM module with an input freq
of 50MHz and an output frequency of 320 MHz. I dont know how to write
the test bench for this(or how to connect the DCM logic to the
propagation delays to get higher output clock frequencies). I'm new
to this technology and would highly appreciate if anyone could help
me with this. the instantiation template is:
dcm1 instance_name (
.CLKIN_IN(CLKIN_IN),
.RST_IN(RST_IN),
.CLKFX_OUT(CLKFX_OUT),
.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
.CLK0_OUT(CLK0_OUT),
.LOCKED_OUT(LOCKED_OUT)
);
and the counter logic is:
module Counter(Clock, Direction, Count_Out);
input Clock;
input Direction;
output [3:0] Count_Out;
reg [3:0] count_int = 0;
always @(posedge Clock)
if (Direction)
count_int <= count_int + 1;
else
count_int <= count_int - 1;

assign Count_Out = count_int;
endmodule

On Tue, 09 Feb 2010 20:11:02 -0600
"Pallavi" <pallavi_mp_at_n_o_s_p_a_m.rediffmail.com> wrote:

Hi,

I'm implementing this project where I've to generate higher output clk
frequencies using DCM module. I have used a counter for delay
generator, for propagation delays(Pls suggest if there is any other
method). I have also instantiated the DCM module with an input freq
of 50MHz and an output frequency of 320 MHz. I dont know how to write
the test bench for this(or how to connect the DCM logic to the
propagation delays to get higher output clock frequencies). I'm new
to this technology and would highly appreciate if anyone could help
me with this. the instantiation template is:
dcm1 instance_name (
.CLKIN_IN(CLKIN_IN),
.RST_IN(RST_IN),
.CLKFX_OUT(CLKFX_OUT),
.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
.CLK0_OUT(CLK0_OUT),
.LOCKED_OUT(LOCKED_OUT)
);
and the counter logic is:
module Counter(Clock, Direction, Count_Out);
input Clock;
input Direction;
output [3:0] Count_Out;
reg [3:0] count_int = 0;
always @(posedge Clock)
if (Direction)
count_int <= count_int + 1;
else
count_int <= count_int - 1;

assign Count_Out = count_int;
endmodule


I know I'm going to regret this. I know you're going to wind up being
some student misunderstanding some inane assignment. But I'm feeling
charitable today and so, against my better judgement, I'm going to try
to walk you back out of the woods.

You're saying you need to generate higher output clock frequencies and
have delays? Why? What is it you're actually trying to design here?
I'm making the possibly over-generous assumption here that you're not
simply throwing logic blocks together in random assortments; what's the
actual goal that you're hoping to wind up with? Because so far what
you're saying doesn't make any sense. Take a step back, describe what
the project is, and maybe someone will be able to get you pointed in
the right direction.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

On Tue, 09 Feb 2010 20:11:02 -0600
"Pallavi" <pallavi_mp_at_n_o_s_p_a_m.rediffmail.com> wrote:

Hi,

I'm implementing this project where I've to generate higher output clk
frequencies using DCM module. I have used a counter for delay
generator, for propagation delays(Pls suggest if there is any other
method). I have also instantiated the DCM module with an input freq
of 50MHz and an output frequency of 320 MHz. I dont know how to write
the test bench for this(or how to connect the DCM logic to the
propagation delays to get higher output clock frequencies). I'm new
to this technology and would highly appreciate if anyone could help
me with this. the instantiation template is:
dcm1 instance_name (
    .CLKIN_IN(CLKIN_IN),
    .RST_IN(RST_IN),
    .CLKFX_OUT(CLKFX_OUT),
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
    .CLK0_OUT(CLK0_OUT),
    .LOCKED_OUT(LOCKED_OUT)
    );
and the counter logic is:
module Counter(Clock, Direction, Count_Out);
    input Clock;
    input Direction;
        output [3:0] Count_Out;
    reg [3:0] count_int = 0;
   always @(posedge Clock)
      if (Direction)
         count_int <= count_int + 1;
      else
         count_int <= count_int - 1;

       assign Count_Out = count_int;          
endmodule

I know I'm going to regret this.  I know you're going to wind up being
some student misunderstanding some inane assignment.  But I'm feeling
charitable today and so, against my better judgement, I'm going to try
to walk you back out of the woods.

You're saying you need to generate higher output clock frequencies and
have delays?  Why?  What is it you're actually trying to design here?
I'm making the possibly over-generous assumption here that you're not
simply throwing logic blocks together in random assortments; what's the
actual goal that you're hoping to wind up with?  Because so far what
you're saying doesn't make any sense.  Take a step back, describe what
the project is, and maybe someone will be able to get you pointed in
the right direction.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

Hello,
Thanks for the reply. This is what the project abstract says:
"FPGA devices are, in general, synchronous machines driven by a system
clock (or several clocks if multiple domains are simultaneously
implemented). Thus, the clock period is the basic unit for measuring time
properties of designs and/or to provide control signals at the outputs.
However, FPGA are equipped (at least potentially) with mechanisms providing
much finer time measurements/generation. For example, by using diversified
propagation delays within the implemented designs it is possible to
generate frequencies that are much higher than the system clock frequency..
The objective of the project is to propose and implement techniques for
generating signals (either frequencies of individual pulses) which are
below the clock period threshold. At the system level, the project consists
in determining propagation delays using programming tools (ISE platform).
At the experimental level, the estimated timing characteristics are to be
verified for repeatability, stability and consistency".
My professor has asked me to propose delay generators(I dont know what that
means). Can you please guide me on this.          

However, FPGA are equipped (at least potentially) with mechanisms providing
much finer time measurements/generation.

For example, by using diversified
propagation delays within the implemented designs it is possible to
generate frequencies that are much higher than the system clock frequency..

The objective of the project is to propose and implement techniques for
generating signals (either frequencies of individual pulses) which are
below the clock period threshold.

At the system level, the project consists
in determining propagation delays using programming tools (ISE platform).

At the experimental level, the estimated timing characteristics are to be
verified for repeatability, stability and consistency".

Hello,
Thanks for the reply. This is what the project abstract says:
"FPGA devices are, in general, synchronous machines driven by a system
clock (or several clocks if multiple domains are simultaneously
implemented). Thus, the clock period is the basic unit for measuring time
properties of designs and/or to provide control signals at the outputs.
However, FPGA are equipped (at least potentially) with mechanisms
providing
much finer time measurements/generation. For example, by using diversified
propagation delays within the implemented designs it is possible to
generate frequencies that are much higher than the system clock frequency.
The objective of the project is to propose and implement techniques for
generating signals (either frequencies of individual pulses) which are
below the clock period threshold. At the system level, the project
consists
in determining propagation delays using programming tools (ISE platform).
At the experimental level, the estimated timing characteristics are to be
verified for repeatability, stability and consistency".
My professor has asked me to propose delay generators(I dont know what
that
means). Can you please guide me on this.

Thank you all for your replies. I discussed with my prof regarding the
project and this is what I'm supposed to do. I have implemented a counter
already. Using the propagation delays for each clock cycle i need to drive
a shift register. That is, this shift register will be having a higher
input clock(330MHZ) than the counter(25MHz). And it will be cleared for the
duration the propagation delay is active for the counter.

Before clearing,
the value needs to be copied to a priority encoder. So finally, the number
of f/fs storing the value times the clock freq in nanoseconds (approx. 3ns
in this case) will be the output. Hope I was able to expalin it properly.
DO I have to write the shift regiater as a different module?

Which type of
register to use for this purpose? How to implement the clearing logic for
shift register considering the propagation delays of counter? Please help
me.

The length of the SR and the width of priority encoder is for me to
decide(8-bit should be sufficient, I guess). Can you please suggest what
should be the appropiate length. To write a testbench the counter and SR
should be in the same module right? Or can we have more than one module
in
a single 'Verilog file'? Please let me know how to use the propagation
delay of counter output to get the clearing logic for SR. The i/p clk for
SR should be a multiple of Counter clk? In that case the clk for SR ca
be
taken as 300Mhz.

I'm implementing this project where I've to generate higher output clk
frequencies using DCM module. I have used a counter for delay generator,
for propagation delays(Pls suggest if there is any other method).