Timing simulation error on bus

Mon Dec 14, 2009 6:42 am   

Hi all,
I am running post route timing simulations for my modules where the
targeted device is Actel proasic3.
I had net list and sdf files for running these simulations.
When running for Min,Typ,Max simulations, i am getting the simulations
results on waveform for only Typ and Max but not for Min. For Min
simulation up to some steps are running and the output bus become idle
until the end of simulation time finishes.
I came to know that by adding 1 ps resolution time then it works,..so
i went for that by giving 1 ps at Modelsim vsim command line its
surprise to see the all results. I am happy but why it is happen for
the Min simulation only ..

Please anyone give some knowledge on this...why it happens

Thanks

Mon Dec 14, 2009 2:06 pm   

On Dec 13, 11:42 pm, JSreeniv <sreenivas.jyo...@gmail.com> wrote:


Presumably because the typ and max simulation models did not try to
delay anything by less than 1 ns but the min simulation did (assuming
that you previously had 1 ns time resolution).

KJ

Mon Dec 14, 2009 5:26 pm   

On Dec 14, 5:06 pm, KJ <kkjenni...@sbcglobal.net> wrote:

Hi KJ,
I am still not getting the reason why it happen, yes as from your
response my previous max and typ simulations are had 1 ns time
resolution.

Thanks

Mon Dec 14, 2009 7:38 pm   

JSreeniv <sreenivas.jyothi_at_gmail.com> writes:


In VHDL, if you specify a time less that the resolution limit, the
simulator turns that into zero time. That means that events which have
a proper ordering when executed with a 1 ps limit:

if rising_edge(clk)
a <= '1' after 100 ps; -- a happend after clk
b <= '0' after 200 ps; -- b happens later than a
end if;

will become equivalent to a system with totally different order

if rising_edge(clk)
a <= '1' after 0 ns;
b <= '0' after 0 ns; -- b,a both happen one delta cycle after clk
end if;

This usually messes things up pretty badly :-)

- Kenn

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