timinganalyzer
Guest
Sun Jan 24, 2010 11:58 pm
Hi All,
Check out the application not "Generate Timing Diagrams directly from
Verilog" at
http://www.timing-diagrams.com/dokuwiki/doku.php?id=app_notes:verilog
As always, suggestions and feedback are welcome.
Dan Fabrizio
The TiimingAnalyzer
www.timing-diagrams.com
testbench
Guest
Mon Jan 25, 2010 7:24 pm
Loved it. I too built similar tool for vera.
One suggestion. The monitoring logic for each signal can be automated
using macros.
Plan to support SystemVerilog too.
Regards,
GopiKrishna
www.testbench.in
On Jan 25, 2:58 am, timinganalyzer <timinganaly...@gmail.com> wrote:
Quote:
timinganalyzer
Guest
Tue Jan 26, 2010 2:21 am
Hi,
Thanks for the macro suggestion. I also want to write a script that
automates the generation of the timing diagram module for a given
signal list. SystemVerilog version is on the to-do list.
-Dan
On Jan 25, 12:24 pm, testbench <k.gopi.kr...@gmail.com> wrote:
Quote:
Loved it. I too built similar tool for vera.
One suggestion. The monitoring logic for each signal can be automated
using macros.
Plan to support SystemVerilog too.
Regards,
GopiKrishnawww.testbench.in
On Jan 25, 2:58 am, timinganalyzer <timinganaly...@gmail.com> wrote:
Hi All,
Check out the application not "Generate Timing Diagrams directly from
Verilog" at
http://www.timing-diagrams.com/dokuwiki/doku.php?id=app_notes:verilog
As always, suggestions and feedback are welcome.
Dan Fabrizio
The TiimingAnalyzerwww.timing-diagrams.com
