Tier Logic introduces the world's first 3D FPGA

Wed Mar 10, 2010 6:46 pm   

The world's first 3D FPGA has arrived! We have a very compelling and
cost effective solution.

Come check it out folks. www.tierlogic.com

Jeff

Wed Mar 10, 2010 7:42 pm   

Jeff,

Except you require registration to even see what it is that you have.

What are you afraid of? Competition?

So, until you decide to stop "qualifying customers" I am afraid you
will remain a relatively unknown company.

That is OK: the longer it takes for you to make money, the more
likely the investors pull the plug, and you go away like all the other
FPGA companies have in the past.

Good luck,

Austin

Wed Mar 10, 2010 7:51 pm   

On Mar 10, 7:42 pm, austin <aus...@xilinx.com> wrote:

100% agree!!

not seen so dumb stupid website launch for a long time

Antti

Wed Mar 10, 2010 8:11 pm   

On Mar 10, 11:46 am, Tier Logic <jeff.ka...@gmail.com> wrote:

Sad.

I have a passing interest in anything proclaiming itself "new" and
"revolutionary" but I won't bother to register to get more
information.

I *might* have the next $1M+ design but it will go to standard FPGAs
because I can't find out about the promising technology on a casual
basis.
___

"Are you interested in dating me?" "Not without a ring." Huh?

Wed Mar 10, 2010 8:25 pm   

On 3/10/2010 4:46 PM, Tier Logic wrote:

Hi Jeff,
I've examined all the old FPGAs I've found in my office, and they all
seem to have three dimensions already. Even the old ones from 1986. This
seems to be the biggest marketing fraud since the film 'The NeverEnding
Story'.
Syms.

p.s. Apologies to Lionel Hutz.

Wed Mar 10, 2010 9:03 pm   

Wow, tough crowd.

http://www.eetimes.com/showArticle.jhtml?articleID=223400002&cid=NL_eet

has some info for the link-inclined. FPGA architecture looks pretty
standard. Value-added is almost entirely in their Tier-FPGA to
Tier-ASIC transition, from what I can tell. Seems to me that that
limits their potential customers-- for really large volume pipelined
life-cycle products, ASIC probably makes sense off the bat. For
low-volume, more specialty products, you're stuck at FPGA timing, so why
not use an FPGA? So you're left with moderate volume customers where
time-to-market drives everything.

I'm not a business head, but I guess if you really got into a groove
with these guys to reduce the FPGA-to-ASIC transition to a couple of
weeks, that could be really cool for some folks.

--Josh


On 3/10/2010 2:25 PM, Symon wrote:

Wed Mar 10, 2010 9:23 pm   

On Mar 10, 1:11 pm, John_H <newsgr...@johnhandwork.com> wrote:

I didn't realize the *entire* site is off limits until you have
registered. Registration means giving them your email address and
waiting for them to get back to you... I guess they want to exclude
the little guys and I am a little guy. So in effect, I don't exist.
To me, they don't exist.

Rick

Wed Mar 10, 2010 10:14 pm   

On Mar 11, 8:25 am, Symon <symon_bre...@hotmail.com> wrote:

Hehe - yes, even Tabula are trying to spin 3D too...

Still, getting back to the site itself, it seems they
have a Stacked-die prototype path, and the main thrust is really mask-
asic.

The stacked die 'emulation devices' will come at a large price
premium, and their config density will need to be low (given this is
top-layer stuff).
I'd expect a power premium too...

The advantage is you CAN get closer to real field emulation, (as
opposed to devices like Atmel's CAPxx, which can only offer bench-
emulation, via a large FPGA)

[" Free NRE
Qualifying production orders of $50k+ for converting an existing
production FPGA to a compatible TierASIC™ device are eligible for free
NRE and conversion."]

That leaves the final chestnuts, of packaging and Price.

One opening I can see in CPLD/FPGA space, is smaller devices with
MORE RAM. - ie really a RAM+CPLD, or
a smart ram, if you like.
That type of product also tends to be somewhat more
stable in code, so could suit TierLogic flows.

Full DualPort memories are very expensive, and large,
and FPGAs have low SRAM levels, until you get very large.

The ProgLogic+Micro space is filling up: Atmel & ST target the
ramping-volume with their MASK variants, and
we have Cypress and Actel with FlashuC+ProgLogic offerings.

-jg

Wed Mar 10, 2010 10:30 pm   

On Mar 11, 5:46 am, Tier Logic <jeff.ka...@gmail.com> wrote:

Pity, rather a bad fumble at first hurdle.

The Prog Logic space is VERY broad indeed, and yet there is NO
indication of which parts of that TierLogic target: Even the simplest
things, like packages and speeds.

Imagine Toyota saying "We have a new product, with 4 wheels - sign up
to learn more". ?!

-jg

Wed Mar 10, 2010 11:41 pm   

On Mar 10, 3:14 pm, -jg <jim.granvi...@gmail.com> wrote:

Stacked die? I read the eetimes article and didn't get anything about
stacked die from Tier Logic. Did I read something wrong? I thought
they were layering TFT on top of the base die to provide the config
memory which takes it out of the base die saving real estate. I am
sure the savings is somewhat mitigated by the need for vias to the
lower layers, but still a 35% (or something like that) savings in size
is nothing to sneeze it. I bet AMD wishes they could get that on
their CPU die right now!



They seem to be pushing their ability to more easily move to ASIC
production, but they seem to offer something to the FPGA only user as
well. I'd be willing to bet there is a premium compared to ASICs so
they are taking a middle ground in that regard.



I'm not clear on what you are saying about this in regards to Tier
Logic.

Rick

Wed Mar 10, 2010 11:54 pm   

On Mar 11, 10:41 am, rickman <gnu...@gmail.com> wrote:

Yes they are, which is why I called it stacked die.
- TWO die flows, one on top of the other.

Base die is made, and then they have a second die-process that is
more complex than just TFT, as it
included connections. [Testing questions remain?]

That will also be why they needed a lot more passes at the TFT
section, as that's where the 'new tech' mostly lies.



A key question here will be: if you are unlikely to
need ASIC, why start with their devices ?


It was a general comment, about where there is space for new-comers,
or new-products in the market.

I've often found RAM dictates the Device choice, more than the Logic.

-jg

Thu Mar 11, 2010 12:29 am   

On Mar 10, 4:54 pm, -jg <jim.granvi...@gmail.com> wrote:

Uh, "stacked die" is normally used to refer to putting two distinct
die mechanically on top of each other. That is a very different thing
than adding processing steps to an existing flow, which is what has
been described for this part.



They claim an advantage in die size which normally translates into a
cost advantage. Of course, the question of cost will be answered when
they start shipping product, or at least quoting prices.



I wish I had that luxury. For me it is typically package since my
designs tend to be size constrained; low pin count (100 or less) in
PCB layout and manufacturing friendly packages are always welcome
(read that as TQFPs or possibly QFNs). Right now I am trying to
squeeze 10 pounds of logic into a 5 pound FPGA because it was the only
one that fit the bill, a bill that was designed a year and a half
ago.

Rick

Thu Mar 11, 2010 1:14 am   

On Mar 11, 11:29 am, rickman <gnu...@gmail.com> wrote:

That depends on where you are in the time-line :)

Years ago, 'stacked die' meant post-wafer assembly using bond-wires &
discrete die, but more modern "nailed stacked die" schemes use vias,
and are done at the wafer level.

ie See this fig2 of "nailed stacked die " here :
http://www.flipchips.com/tutorial71.html

and compare with the image here :

http://www.tierlogic.com/uploads/press-room-files/Tier-Logic-Cross-Sections-of-TierFPGA-and-TierASIC-Devices.pdf

The 'different process', and multiple Transistor planes, is now more
a distinguishing feature, than a literal interpretation of 'die'.

Tierlogic are quite clear they use Stacked (different) processes, and
via type contacts.

Doing the stacking at the wafer/fab level saves handling, but you are
exposed to testing issues.

Until you have finished the two-process flows, you really have
nothing to test. So yields are ??

Default TFT flows are also higher voltage, and relatively coarse
grained.
So the bit-counts will be interestng to see, when
they are finally revealed.

-jg

Thu Mar 11, 2010 7:45 am   

austin wrote:


At least they don't require NDAs etc. for basic information. I don't
see any problem in registration or even NDAs. A and X also require
NDAs before they tell anything about their future products.


Possibly yes. The big guys are very happy to steal the good ideas of
the smaller ones and use their muscle to push the innovations to
their products, and the original inventor gets nothing (unless
they vere good at patenting it).


A and X qualify also customers for early access etc. And for a small
startup the qualifying is even more important, they don't have the
muscle to support big amount of customers.


The money is not in the hobbyist market but on the big accounts. And
big accuounts have no problem with registration, NDAs etc.


--Kim

Thu Mar 11, 2010 7:54 am   

-jg wrote:

I don't see it impossible to test the cmos wafer before the tft process,
depending on how they constructed the topmost metal layer. For example
they could have some dummy bump pads there for power, and then internal
bist with certain coverage built with the lower metal layers.

FPGAs are quite easy in terms of yield, because you can have redundant
structures for yield improvement (in fabric and in memories).

--Kim