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Tier Logic
Guest
Thu Mar 11, 2010 9:41 am
On Mar 10, 10:54 pm, Kim Enkovaara <kim.enkova...@iki.fi> wrote:
Quote:
-jg wrote:
Doing the stacking at the wafer/fab level saves handling, but you are
exposed to testing issues.
Until you have finished the two-process flows, you really have
nothing to test. So yields are ??
I don't see it impossible to test the cmos wafer before the tft process,
depending on how they constructed the topmost metal layer. For example
they could have some dummy bump pads there for power, and then internal
bist with certain coverage built with the lower metal layers.
FPGAs are quite easy in terms of yield, because you can have redundant
structures for yield improvement (in fabric and in memories).
--Kim
I don't want to marketeer too much here because this is a technical
site. All I can tell you is that our FPGAs will save you money because
our die size is reduced. If you convert it to our ASIC you will save
even more money for a minimal NRE. ( zero NRE for early access
customers).
I did want to clear up any questions on our testing methodolgies.
Our FPGA is tested the same as any other SRAM based FPGA is tested.
The only difference is that our configuration SRAM is above the CMOS
base layer in a second active layer resulting in a smaller die size.
We test it to 100% functional FPGA test patterns in the same way any
other SRAM-based FPGA is tested. There is no need to test until the
complete FPGA is done being processed.
The TierASIC is tested with a scan-based ASIC methodology we added to
the silicon. The customer is not required to generate any test
vectors. Once you lock your design, you simply send us the bitstream
and we auto generate the test vectors for your ASIC. We create one M9
hard mask and stop there. I do believe that the significant cost
reduction in moving from our FPGA to our ASIC will make it a popular
choice. You also get the advantages of no possibility of configuration
SEUs, bitstream security, no config rom needed, instant on, and
customer logos.
The yield of the ASIC increases over the yield of the FPGA because the
ASIC is only tested to that customer pattern. Also, the timing is
identical to the FPGA version which means zero conversion risk. We can
deliver ASIC samples in about 4 weeks.
Jeff
John_H
Guest
Thu Mar 11, 2010 4:12 pm
On Mar 11, 1:45 am, Kim Enkovaara <kim.enkova...@iki.fi> wrote:
Quote:
big accuounts have no problem with registration, NDAs etc.
--Kim
That's a false assumption. Even big accounts have individual
engineers who thrive on free flow of information to
understand the
technologies to consider in the first place. There is a tendency
not to look into every company proclaiming new and revolutionary
technology if the information isn't readily available.
Perhaps some engineers are interested in spending the time and hassle
to dig into all the little wannabe startups but there are few that
warrant the all-out risk associated with a new single-source supplier
with no guaranteed future unless the technology is truly superb. If
the risk is extreme, why look at it in the first place unless it's a
casual 15 minutes of web perusal to understand the claims?
John_H
Guest
Thu Mar 11, 2010 4:32 pm
On Mar 11, 2:41 am, Tier Logic <jeff.ka...@gmail.com> wrote:
Quote:
On Mar 10, 10:54 pm, Kim Enkovaara <kim.enkova...@iki.fi> wrote:
-jg wrote:
Doing the stacking at the wafer/fab level saves handling, but you are
exposed to testing issues.
Until you have finished the two-process flows, you really have
nothing to test. So yields are ??
I don't see it impossible to test the cmos wafer before the tft process,
depending on how they constructed the topmost metal layer. For example
they could have some dummy bump pads there for power, and then internal
bist with certain coverage built with the lower metal layers.
FPGAs are quite easy in terms of yield, because you can have redundant
structures for yield improvement (in fabric and in memories).
--Kim
I don't want to marketeer too much here because this is a technical
site. All I can tell you is that our FPGAs will save you money because
our die size is reduced. If you convert it to our ASIC you will save
even more money for a minimal NRE. ( zero NRE for early access
customers).
I did want to clear up any questions on our testing methodolgies.
Our FPGA is tested the same as any other SRAM based FPGA is tested.
The only difference is that our configuration SRAM is above the CMOS
base layer in a second active layer resulting in a smaller die size.
We test it to 100% functional FPGA test patterns in the same way any
other SRAM-based FPGA is tested. There is no need to test until the
complete FPGA is done being processed.
The TierASIC is tested with a scan-based ASIC methodology we added to
the silicon. The customer is not required to generate any test
vectors. Once you lock your design, you simply send us the bitstream
and we auto generate the test vectors for your ASIC. We create one M9
hard mask and stop there. I do believe that the significant cost
reduction in moving from our FPGA to our ASIC will make it a popular
choice. You also get the advantages of no possibility of configuration
SEUs, bitstream security, no config rom needed, instant on, and
customer logos.
The yield of the ASIC increases over the yield of the FPGA because the
ASIC is only tested to that customer pattern. Also, the timing is
identical to the FPGA version which means zero conversion risk. We can
deliver ASIC samples in about 4 weeks.
Jeff
Thanks for returning to talk further about the issues brought up on
this newsgroup.
I wish you success in achieving noticeable market share.
While I can understand the savings brought from removing the
configuration memories and associated die size, I still envision the
FPGA-like overhead as being significant since routing is such a large
portion of typical FPGA resources. The routing won't go away, only
the configuration memory. The result is still not an ASIC-killer
unless the price-point for (for instance) 40nm TierASIC devices can
compare at a price point with a couple steps behind in the process
curve.
If a turn on a 90nm or 120nm ASIC can produce similar cost points in
per-piece costs to a TierASIC on the tighter process, there might be
something here. We all understand the issues of NRE and timing. But
it's so much smoke and mirrors at this point it's hard for the big
customers who have ASIC suppliers or the medium customers who need to
*work* to get access to information to really consider the technology.
If the TierASIC information becomes more transparent to demonstrate
the true "technical" savings versus the ASIC approach rather than
"marketing" savings, TierASIC won't disturb the engineers responsible
for *considering* the technology in the first place. Marketing people
tend not to sway engineers with marketing; they tend to influence with
the technology proposition and real associated cost points.
In my mind, it's a question of whether there's a desire to market to
the select few who aren't concerned about risk versus reward within
their company framework or to the many who may see how large the
reward is and how low the risk is in the end.
I want better solutions to succeed. *I* won't pursue vague promises
but I'll consider real information. Big difference.
austin
Guest
Thu Mar 11, 2010 6:23 pm
John,
Correct, you got it.
I was always looking for the best solution when I did my stint as a
design engineer from 1978 to 1998 in telecom.
The last thing on my list was the vendor: there were many things
ahead of that (although, the vendor, and their history is important,
too).
So, in the telecoms business: here was my order of importance:
1. Price
2. Price
3. Price.
4. Power: (yes, even so long ago, telecoms were 'green')
5. Availability: (if it had the advantages above, I would pre-order,
stock, and do whatever needed to get those advantages)
6. Performance (I would make do with less performance if I had the
advantages above)
7. Reliability: (I would burn in, re-test, operate at a lower
temperature, if I could get an inexpensive part to meet my 20 year
life requirement)
8. Vendor: (support, applications notes, demo boards, free IP, code,
tools -- I would tolerate a lot missing here to meet the first three
goals)
The bottom line was if I could make an equivalent, or better product,
for a lower cost than my competition, I would get the contract.
I once lost a million dollar contract to MCI being just $0.01 more
expensive on a $125 circuit pack than my competition, so it was (and
still is) a rough real world out there.
So, for those who used to do what I did, log onto their website, give
them the required information, download the information, and get
going.
Austin
Nico Coesel
Guest
Thu Mar 11, 2010 6:59 pm
John_H <newsgroup_at_johnhandwork.com> wrote:
Quote:
On Mar 10, 11:46=A0am, Tier Logic <jeff.ka...@gmail.com> wrote:
The world's first 3D FPGA has arrived! We have a very compelling and
cost effective solution.
Come check it out folks.www.tierlogic.com
Jeff
Sad.
I have a passing interest in anything proclaiming itself "new" and
"revolutionary" but I won't bother to register to get more
information.
I *might* have the next $1M+ design but it will go to standard FPGAs
because I can't find out about the promising technology on a casual
basis.
I agree. We use a 1000+ ARM controllers per year. Luminary required
registration so they didn't even make it on the short list.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico_at_nctdevpuntnl (punt=.)
--------------------------------------------------------------
-jg
Guest
Thu Mar 11, 2010 9:08 pm
On Mar 12, 3:32 am, John_H <newsgr...@johnhandwork.com> wrote:
Quote:
The TierASIC is tested with a scan-based ASIC methodology we added to
the silicon. The customer is not required to generate any test
vectors. Once you lock your design, you simply send us the bitstream
and we auto generate the test vectors for your ASIC.
The claim of Auto-generate test vectors is interesting.
Who pays for < 100% coverage 'issues' ?
Quote:
While I can understand the savings brought from removing the
configuration memories and associated die size, I still envision the
FPGA-like overhead as being significant since routing is such a large
portion of typical FPGA resources.
The memory has not gone away, in the FPGA flow is it
merely stacked, so die size has shifted to more process steps. Raw
silicon is actually quite cheap.
Even in their ASIC flow, that 'memory ghost' remains, as the die size
is locked to the larger of the two possible choices. Their fpga to
asic step saving
is some process steps, testing savings, and yield gains
as they hope you are not using defects.
Where die size savings really kick in, is when they allow MORE logic
into what is a 'practical size ceiling' - but we still have no
indications of WHO their customers are ? - no logic or package info ?.
If your package is IO bound, then die size claims are
totally illusory.
-jg
Kim Enkovaara
Guest
Fri Mar 12, 2010 7:14 am
-jg wrote:
Quote:
The claim of Auto-generate test vectors is interesting.
Who pays for < 100% coverage 'issues' ?
When have you seen ASIC with 100% test coverage. It is either
impossible or the amount of vectors would be so huge that the
tester time would make the chip very expensive. Tester time
is quite big part of the chip price.
Quote:
merely stacked, so die size has shifted to more process steps. Raw
silicon is actually quite cheap.
Wafers are not that cheap. Altough big part of the cost are the
process steps trough the fab.
Quote:
If your package is IO bound, then die size claims are
totally illusory.
You can pack IOs also inside the die, not only to the boundaries.
IO bound vs. logic bound problems have diminished with some cell
libraries.
--Kim
Peter Alfke
Guest
Fri Mar 12, 2010 9:33 pm
From the official TIER website:
"Support:
Tier Logic intends support to be a differentiator from the mainstream
FPGA vendors, who increasingly focus their support on only a few
select customers, ignoring or providing poor-quality support to all
but their largest accounts. Our approach is not to attempt to support
thousands of customers, but to sign up to deliver high-quality support
to every customer with whom we engage.
Please register to get full access to the Tier Logic website."
Peter says:
They hired a 13-year Altera veteran as VP of marketing and sales.
Where did he pick up such contorted writing and negative reasoning ?
It is unprofessional, to say the least.
rickman
Guest
Sat Mar 13, 2010 5:05 am
On Mar 11, 9:32 am, John_H <newsgr...@johnhandwork.com> wrote:
Quote:
I want better solutions to succeed. *I* won't pursue vague promises
but I'll consider real information. Big difference.
I am also glad to hear from the Tier representative. I don't think of
discussing the technical issues of their product to be spamming, even
if it is from a "marketing" perspective.
As to the "vague" promises, the bottom line of what Tier is offering
is price... and we won't know that until we actually have a chance to
compare apples to apples. Heck, you can't even compare Xilinx and
Altera until you get them both in your office (tagging along with the
local disti) and get hard quotes. We all know how there is no such
thing as "list" price when it comes to used cars or FPGAs. In that
regard, Tier is no different than X or A or L or the other A.
Rick
rickman
Guest
Sat Mar 13, 2010 5:11 am
On Mar 11, 2:08 pm, -jg <jim.granvi...@gmail.com> wrote:
Quote:
On Mar 12, 3:32 am, John_H <newsgr...@johnhandwork.com> wrote:
The TierASIC is tested with a scan-based ASIC methodology we added to
the silicon. The customer is not required to generate any test
vectors. Once you lock your design, you simply send us the bitstream
and we auto generate the test vectors for your ASIC.
The claim of Auto-generate test vectors is interesting.
Who pays for < 100% coverage 'issues' ?
While I can understand the savings brought from removing the
configuration memories and associated die size, I still envision the
FPGA-like overhead as being significant since routing is such a large
portion of typical FPGA resources.
The memory has not gone away, in the FPGA flow is it
merely stacked, so die size has shifted to more process steps. Raw
silicon is actually quite cheap.
Even in their ASIC flow, that 'memory ghost' remains, as the die size
is locked to the larger of the two possible choices. Their fpga to
asic step saving
is some process steps, testing savings, and yield gains
as they hope you are not using defects.
Where die size savings really kick in, is when they allow MORE logic
into what is a 'practical size ceiling' - but we still have no
indications of WHO their customers are ? - no logic or package info ?.
If your package is IO bound, then die size claims are
totally illusory.
-jg
Even if any given device size is IO bound, there is still a savings if
they are able to build the same capacity using an more mature and less
expensive processing technology. I seem to recall some number being
quoted on a process that is not near the 45 nm currently used in
FPGAs. I am sure their first devices won't be using the most
expensive processes.
Rick
rickman
Guest
Sat Mar 13, 2010 5:17 am
On Mar 12, 2:33 pm, Peter Alfke <al...@sbcglobal.net> wrote:
Quote:
From the official TIER website:
"Support:
Tier Logic intends support to be a differentiator from the mainstream
FPGA vendors, who increasingly focus their support on only a few
select customers, ignoring or providing poor-quality support to all
but their largest accounts. Our approach is not to attempt to support
thousands of customers, but to sign up to deliver high-quality support
to every customer with whom we engage.
Please register to get full access to the Tier Logic website."
Peter says:
They hired a 13-year Altera veteran as VP of marketing and sales.
Where did he pick up such contorted writing and negative reasoning ?
It is unprofessional, to say the least.
I hadn't seen that. I don't see this as "contorted", but rather very
well stated without raising alarms. It is saying, without being a
blunt instrument, that they are going to support all of their
customers, but they are going to be choosy about their customers.
They won't have thousands to support because they won't have thousands
of customers. That sounds like the course TI has always taken with
their automotive product lines, including their original ARM devices,
that you couldn't even get a data sheet on unless you could show you
would be buying millions. I ran into this wall with TI once.
Rick
Raymund Hofmann
Guest
Sun Mar 14, 2010 1:06 am
On 10 Mrz., 17:46, Tier Logic <jeff.ka...@gmail.com> wrote:
Quote:
The world's first 3D FPGA has arrived! We have a very compelling and
cost effective solution.
Come check it out folks.www.tierlogic.com
In my effort checking this out i also checked out:
www.easic.com
Promises to reduce the power&area problem of SRAM-FPGA by routing a
"FPGA-like" structured master with a via layer manufactured by e-beam
lithography.
They claim "no NRE" FPGA-like development, but it looks like more work
and more expensive to me.
But can be considered reprogrammable, if you have a few weeks and
money for each reprogramming.
nupga.com
I guess they rather look for licensees of their reprogrammable
antifuse technology.
But then a very similar approach as Tierlogic, also called 3D.
Andy Peters
Guest
Mon Mar 15, 2010 7:29 pm
On Mar 12, 12:33 pm, Peter Alfke <al...@sbcglobal.net> wrote:
Quote:
From the official TIER website:
"Support:
Tier Logic intends support to be a differentiator from the mainstream
FPGA vendors, who increasingly focus their support on only a few
select customers, ignoring or providing poor-quality support to all
but their largest accounts. Our approach is not to attempt to support
thousands of customers, but to sign up to deliver high-quality support
to every customer with whom we engage.
Please register to get full access to the Tier Logic website."
Peter says:
They hired a 13-year Altera veteran as VP of marketing and sales.
Where did he pick up such contorted writing and negative reasoning ?
It is unprofessional, to say the least.
So, maybe the first response to ANY WebCase/support question won't be,
"Please send us your design."
-a
rickman
Guest
Mon Mar 15, 2010 9:11 pm
On Mar 15, 1:29 pm, Andy Peters <goo...@latke.net> wrote:
Quote:
On Mar 12, 12:33 pm, Peter Alfke <al...@sbcglobal.net> wrote:
From the official TIER website:
"Support:
Tier Logic intends support to be a differentiator from the mainstream
FPGA vendors, who increasingly focus their support on only a few
select customers, ignoring or providing poor-quality support to all
but their largest accounts. Our approach is not to attempt to support
thousands of customers, but to sign up to deliver high-quality support
to every customer with whom we engage.
Please register to get full access to the Tier Logic website."
Peter says:
They hired a 13-year Altera veteran as VP of marketing and sales.
Where did he pick up such contorted writing and negative reasoning ?
It is unprofessional, to say the least.
So, maybe the first response to ANY WebCase/support question won't be,
"Please send us your design."
Yeah, but put yourself in their shoes. I'd hate to respond to calls
saying, "It doesn't work when I do this". "Well don't do that!" Talk
about your thankless jobs!
Rick
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