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The meaning and usage of `celldefine macro in Verilog

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elektroda.net NewsGroups Forum Index - Verilog Language - The meaning and usage of `celldefine macro in Verilog

Quang Anh
Guest

Thu May 24, 2007 5:33 pm   



Hello all,

I'm just a beginner in Verilog. Yesterday, I read a design containing
many `celldefine macros. For example,
`celldefine
module and21 (A1, B1, Y1);
input A1, B1;
output Y1;
wire A1, B1, Y1;
and #(0.0, 0.0) and_cell (Y1, A, B);
`endcelldefine

But I do not know much about this type of macro in Verilog. I searched
on Internet for a while, and all what I got is just that this macro is
used to mark a module as a cell module, and cell modules are used by
PLI rountines. In coclusion, my current understanding on this is very
shallow.

Who experienced on this point, please teach me in more detail.
I'm looking forward to any information from you.

Sincerely yours,
Quang Anh


Guest

Thu Nov 03, 2016 7:09 pm   



Il giorno giovedì 24 maggio 2007 18:33:59 UTC+2, Quang Anh ha scritto:
Quote:
Hello all,

I'm just a beginner in Verilog. Yesterday, I read a design containing
many `celldefine macros. For example,
`celldefine
module and21 (A1, B1, Y1);
input A1, B1;
output Y1;
wire A1, B1, Y1;
and #(0.0, 0.0) and_cell (Y1, A, B);
`endcelldefine

But I do not know much about this type of macro in Verilog. I searched
on Internet for a while, and all what I got is just that this macro is
used to mark a module as a cell module, and cell modules are used by
PLI rountines. In coclusion, my current understanding on this is very
shallow.

Who experienced on this point, please teach me in more detail.
I'm looking forward to any information from you.

Sincerely yours,
Quang Anh


Hello, it is a library cell model, a behavioural description of the specific element the foundry can provide you.
Hope this helps,
best regards,
Marcello

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