Test Bench Time unit problem

Tue May 18, 2010 7:57 am   

Hi,

I am facing an issue in Clock generation using my Verilog Testbench.

I am generating clock using

assign clk_final = clk_stb and clk_enable

always begin

if (clk_final == 1'b0)
clk_usim_stb <= #(10.416) 1'b1;
else clk_usim_stb <= #(10.416) 1'b0;
@(clk_final);

end

(clk_final is 0 intially)

The problem I am facing is I am getting clock with a period/2 of only
10 ns . I tried giving 10.5 (10.6, 10.7 etc)...In these cases I am
getting period/2 of 11 ns.....i.e. I am not able to get the actual
desired clock. The clock period is getting rounded up.

I am also providing the following in my Testbench

`timescale 1ns/1ps
initial $timeformat(-9, 1, " ns", 12);

Please can someone help me understand if this is my testbench problem
or my simulator problem... I am using Verdi for opening this fsdb file
dump.


Thanks
Verilog Baby

Sat May 29, 2010 1:36 am   

On May 18, 12:57 am, Melvin <whereismel...@gmail.com> wrote:

If your time precision is 1ps, delays should not be getting rounded to
1ns.

The $timeformat call does not affect delays, only the format that
times are printed in.

Assuming that you have set the timescale as you have described, this
could be a problem with your simulator. Or it might be an issue with
your waveform viewer, which could be rounding the times
before showing them to you. To rule out this possibility, I would
suggest using a different mechanism to see what times the signal is
changing at.

Sat May 29, 2010 6:21 am   

On May 18, 12:57 am, Melvin <whereismel...@gmail.com> wrote:

Maybe it's a stupid question, but I don't see how clk_usim_stb
loops back to clk_final. Is clk_stb assigned to clk_usim_stb?
If it is, is it assigned in the same module?