Tabula. (FPGA start up)

Tue Mar 02, 2010 12:22 pm   

This lot seems to be revealing a bit more about their stuff.

http://www.mercurynews.com/breaking-news/ci_14493616

http://www.tabula.com

Tue Mar 02, 2010 1:04 pm   

On Tue, 02 Mar 2010 11:22:07 +0000, Symon wrote:


Thanks for the heads-up. Any startup may simply vanish
without trace in a puff of hot air, but this lot look as
though they may have one of the few really innovative
and potentially disruptive ideas to hit FPGAs in recent
times.

Commercial reality being what it is, it is unlikely that
hobbyists and small design shops will be able to get their
hands on real tools and devices at a sensible price for
quite some time. But I reckon it's still worth watching.
--
Jonathan Bromley

Tue Mar 02, 2010 6:39 pm   

All,

Yes, Tabula is in the sunshine of the vulture capital technology
rollout phase.

I like the FPGA Journal's characterization of the technology
announcements: been there, done that, and when you ship the parts,
let me know.

However, it is a necessary part of doing business that you attempt to
generate excitement for a new product.

I will suggest to you that you go back and read all the hype, up until
now, as it does tell a better story of what is going on. For example,
originally, the technology was better in cost, speed, and power (how
they got their funding). Then, after awhile, cost, maybe speed (in
some applications), and power. In the latest release, we see cost,
maybe speed, and power will be the same or worse.

"There ain't no such thing as a free lunch" (TANSTAAFL), and if you
can context switch at 1.6 GHz, with 8 time slices, then you have a 200
MHz fabric which is somewhat smaller (not 8, but perhaps 6?) than a
comparable run of the mill FPGA device.

With the added dynamic power (CV^2F), since the capacitance of the
interconnect is based on its length, and their claim is that the
length of interconnect in their devices is 1/5th that of a comparable
device, we can suppose that C is 1/5th. Given that they ALWAYS switch
at 1.6 GHz some nodes, and they have announced that power is not one
of the benefits any longer, we can pretty much conclude that because
of the time slicing, the improvement in interconnect didn't pan out
and result in a cost savings, but came in as a wash, or perhaps worse.

In order to operate at 1.6 GHz, they have to have all the transistors
be really fast, which means really leaky, so perhaps their static
power is out of control, as well. In a comparable 'old style' FPGA
device, many transistors may be lower leakage, as they don't switch
that fast. Of course, we may have 5 times as many devices as the
Tabula chip, but they may have 10 times less leakage.

Is there a targeted market? You bet, they have aimed at the
"networking high end" which is the bread and butter of the big
players! Will they actually meet the requirements? What is the
reliability? What is their soft error behavior? What happens when
the design doesn't work: how do you debug the "magic" they perform by
re-interpreting your HDL code?

It will be interesting: is this just an excuse to buy really nice
cars, and get fat paychecks, until it all blows up? Or, is this a
novel, and game-changing technology?

Having been part of the SIlicon Valley community since 1978, this is a
very familiar tune, and how it plays out may not be such a surprise to
anyone (except the investors).

I have to say, they have a stellar group of people, ex-Xilinx, and ex-
Altera both.

Austin

Tue Mar 02, 2010 9:15 pm   

On Tue, 2 Mar 2010 11:28:02 -0800 (PST), Eric Smith wrote:


Nicely put, but that way lies stagnation and the
ultimate death of our industry. Sometimes there will
be a truly novel, industry-regenerating idea out there.
No-one can reliably guess which one of the ideas will
be that mould-breaker, but it is important to stay
aware of the possibilities.

There are domains where there appears to have been
continuous steady improvement - semiconductor wafer
size getting bigger, design rules getting smaller,
hard disk capacity getting bigger and cheaper -
but those progressive improvements are not truly
progressive; they are fuelled by discontinuous
changes (the discovery and exploitation of
GMR-effect in disk drives, for example). You
don't immediately see a huge stepwise change
because of these innovations; there's no point
in creating something that's 10 times as good as
the competition, when something 1.5 times as good
will make you rich. So it appears to the casual
or ill-informed observer that things just go on
getting better without innovation, when in truth
it is innovation (and the pull of consumer demand)
that drives it all.

Good luck to Tabula. They must play the game by the
rules, and they are up against unfair odds - just count
the number of FPGA vendors, many of them genuinely
innovative, who have fallen by the wayside. But they
just might be on to something. And, as Austin concludes,
they have a dream team. They won't beat Xilinx at their
own game, but they just might be writing the rules of
a completely new game.
--
Jonathan Bromley

Tue Mar 02, 2010 9:28 pm   

On Mar 2, 8:39 am, austin <aus...@xilinx.com> wrote:

Reminds me of some of the players that tried to compete with Intel on
high-end x86 processors. Only AMD has been successful at that. Your
technical advantages will no longer be advantages by the time you get
the product to market.

A friend was an engineer at one of the companies that tried it back in
the late 486 era. He called that business plan "running ahead of the
steamroller". The steamroller doesn't seem to move that fast, so you
can run ahead of it for a while, but you get tired before the
steamroller does.

Tue Mar 02, 2010 11:22 pm   

On 2 Mar, 11:22, Symon <symon_bre...@hotmail.com> wrote:

Looks interesting. Increasing transistor speed with lower power is
advancing, but reducing interconnect R and C seems to be at a limit of
copper thickness. The copper can be thickened up to limits.

The flop 4LUT mux thing with is a 7LUT * 8 with simple time rotary mux
may be. Then it's just lower interconnect density and length. Umm have
to wait and see.

cheers Jacko

http://forum.nibzx.co.uk - general technical forum

Tue Mar 02, 2010 11:28 pm   

On Mar 3, 12:22 am, Symon <symon_bre...@hotmail.com> wrote:

Time will tell....

meanwhile, over in the other corners, anyone remember Triscend ?

Well, others are having a crack at the same market, but
slightly updated, for 2010.

See Cypress PSoC5 (Data, no open samples yet) and the just unveiled
Actel A2F200 (supposedly real silicon & Eval)

These both bundle a FLASH Cortex uC with Analog and FPGA fabric.

Sounds great on a marketing-lunch-napkin, but the fish-hook in this
has always been price, and the conflict of constrain of
Flash.Ram.cells.

The sampling smaller sibling, the PSoC3 has moved to ~$20 in price
indicators, and the A2F200 is showing ~$40 (no indications yet of the
A2F060)

You can get a choice of ARM core, for $1-$3, and a choice of CPLD-
FPGA for $3-$6, so that single-package-premium really narrows down the
customers.

-jg

Wed Mar 03, 2010 3:03 am   

On Mar 3, 12:22 am, Symon <symon_bre...@hotmail.com> wrote:

A better overview is here
http://www.eetasia.com/ART_8800599499_499495_NT_b33fb563_2.HTM

Some of what Tabula say, reads more like a patent dance, than any
technical explanation.

So, it is locally 1.6GHz, with time-sliced threads.
It might save Logic and routing, but it will have no config-memory
saving, and it ADDS the complexity of
rapid config multiplex. (not to mention power impacts)

We already have Achronix climing 1.5GHz PLDs since 2008, and XMOS
have 400-500Mhz hard-time-sliced cores shipping also.

Tabula have some rather quaint terminology, as they try to spin what
they do, but designers have always tried to do more serially &
pipeline, to save resource, if they can.

It seems their SW will do the 'thread slice & dice' for you, and that
may be the critical point.

If that works, and you can debug it, it could be useful. If it fails,
it will fail in a tangle.

-jg

Thu Mar 04, 2010 2:46 pm   

On Mar 2, 12:15 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

I wasn't suggesting that it is completely impossible to outrun the
steamroller, but if you want a much better chance of doing it, you
should try running in a different direction than the steamroller is
going. If you are only slightly off the path of the steamroller,
maybe it will shift its path a bit to follow you, and maybe not. If
your path is significantly different from that of the steamroller,
there's a better chance that it will ignore you.

Other than AMD, the companies that have any success selling x86
processors are targeting niches that Intel didn't focus much effort
on, rather than trying to compete with Intel's mainstream parts. Most
of them are targetting embedded and low power designs, where Intel's
offerings were traditionally weak, though Intel seems to have become
much more interested in those in the last few years. Many of those
companies, including the one my friend worked at, started their x86
designs with the intent of competing at the high end, and ultimately
realized that they couldn't.

If you're going to compete with big FPGA vendors, there had better be
something that your FPGA is *significantly* (not just slightly) better
at than their parts. Whether Tabula's stuff is sufficiently better
remains to be seen.


If you're one of the big players, 1.5 times better might be good
enough to gain you a bit of market share, but it rarely is sufficient
for a startup to gain traction against the big guys. And startups
that plan on being 10x better are often not even 1.5x better by the
time they ship product. Successful startups usually have something
that is *many* times better than the existing products, on some axis
almost entirely orthogonal to the prior metrics.

Eric

Fri Mar 05, 2010 1:06 am   

On Mar 2, 2:28 pm, Eric Smith <space...@gmail.com> wrote:

You call that success??? AMD is losing money hand over fist and there
is no relief in sight! At one time they played leap frog with Intel
in terms of who had the fastest parts, bragging rights and therefore
higher average selling prices. But AMD has been sucking wind for more
years than the cycles used to take. They are a full generation of
process technology behind. They had to sell off their fabs to raise
cash to stay afloat. Unless AMD has some really big trick up their
sleeve (something better than a one time payment from Intel which
makes up for maybe one year's losses) they are going to go the way of
Zilog. Personally, I don't see them surviving, at least well enough
to actually make an impact in the market. Intel may keep them around
just to keep the FTC off their aggressive and illegal pricing backs.

Rick

Fri Mar 05, 2010 1:29 am   

On 3/4/2010 12:46 PM, Eric Smith wrote:

Mate,
Ever wonder if you've been doing this too long? Did you write that last
phrase with a straight face?
Cheers, Syms.

Fri Mar 05, 2010 1:31 am   

On 3/4/2010 11:06 PM, rickman wrote:


Yep.

http://www.theregister.co.uk/2009/11/18/amd_to_pay_down_debt/

Fri Mar 05, 2010 1:40 am   

On Mar 2, 4:28 pm, -jg <jim.granvi...@gmail.com> wrote:

Yeah, I have been watching the Cypress stuff and I am not overly
impressed. I guess the new stuff far outdoes the PSOC1, but at those
prices they are addressing a totally different market and likely will
only find a home in very space constrained designs.

I just heard about the Actel parts and they seem interesting. But I
bet they bring a seriously painful price. That will be the
determiner. The PSOC3/5 and Actel SmartFusion parts are also very
different in size with Actel SmartFusion coming in a 256 BGA at the
smallest and the PSOC3/5 a 100 pin package at the largest IIRC.

Other FPGAs don't do analog so well, but they can be used with a soft
processor to compete with the low end of these parts.

Rick

Rick

Fri Mar 05, 2010 1:43 am   

On Mar 2, 8:03 pm, -jg <jim.granvi...@gmail.com> wrote:

Yeah, a lot of their success will depend on the tools. Not only do
they need to work, they need to be usable. I am trying to think how
to write VHDL for hardware that really is sequential as well as
concurrent.

Rick

Fri Mar 05, 2010 2:22 am   

On Mar 5, 12:43 pm, rickman <gnu...@gmail.com> wrote:

I'm exercising the XMOS devices currently, and they are certainly
interesting devices.
They have a truly hard/deterministic threaded core
and some quite good tools.
Sadly, the Docs are scattered and read like an in-joke.
(and on a device as left-field as XMOS, knowing what
it can & can't do, is important)

I am currently seeing if a design that is CPLD+RAM, can work on XMOS.
RAM in there is easy, (way more than any similar priced CPLD/FPGA) but
hitting the speed targets in SW, is 'interesting', but by careful
slice into threads, it might just make it. 4 threads come at zero
speed cost, as do 32 bit datapaths.

Tabula's approach seems a morph of this. It should work well on code
that needs to be hard-deterministic, and that can serialize nicely to
shrink logic.

Something like Base-station math-ops would be a good market
footprint, and it is unlikely to be low power.
Memory&bandwidths will be the other key factors.

-jg