system verilog ques. Is there a separate newsgroup for syste

Thu Feb 10, 2011 2:47 am   

rand bit [7:0] byte0;
rand bit [7:0] byte1;

The following constraint works:
constraint xyz {
(byte0 >='h41 && byte0 <='h5a) -> byte1
inside {['h41:'h5a]};
(byte0 >='h61 && byte0 <='h7a) -> byte1
inside {['h61:'h7a]};
}

But I want to modify it to something to this effect:
constraint xyz {
(byte0 >='h41 && byte0 <='h5a) -> byte1
inside {['h41:'h5a]} else byte1 inside {['h7b,'h7f]};
(byte0 >='h61 && byte0 <='h7a) -> byte1
inside {['h61:'h7a]} else byte1 inside {['h7b,'h7f]};
}

I get a syntax error for this. What is the correct syntax for this if
it can be done inside a constraint? Or any other suggestion how it can
be done?

Thanks.

Thu Feb 10, 2011 1:11 pm   

masoodtahir <masoodtahir_at_hotmail.com> writes:


See LRM (18.5.5 Implication)

,----
| constraint xyz {
| if (byte0 >='h41 && byte0 <='h5a)
| byte1 inside {['h41:'h5a]}
| else byte1 inside {['h7b,'h7f]};
| if (byte0 >='h61 && byte0 <='h7a)
| byte1 inside {['h61:'h7a]}
| else
| byte1 inside {['h7b,'h7f]};
| }
`----

Regards
Marcus

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