EDAboard.com | EDAboard.eu | EDAboard.de | EDAboard.co.uk | RTV forum PL | NewsGroups PL

System Verilog 2D input port?

Ask a question - edaboard.com

elektroda.net NewsGroups Forum Index - Verilog Language - System Verilog 2D input port?

John Smith
Guest

Thu Nov 25, 2010 4:46 am   



Is it acceptable to have 2D input ports using System Verilog?

I know it's not possible in Verilog. The only workaround I could think
of is to 'flatten' out the input port and use it; but that seems to be
messy inside loops. Is there any other workaround?

unfrostedpoptart
Guest

Thu Nov 25, 2010 6:29 am   



On Nov 24, 6:46 pm, John Smith <redditor...@gmail.com> wrote:
Quote:
Is it acceptable to have 2D input ports using System Verilog?

Sure. It allows just about anything: arrays, structures, interfaces
(obviously). Now, whether your synthesis tool handles these
constructs is another question that needs to be asked of the vendor.

elektroda.net NewsGroups Forum Index - Verilog Language - System Verilog 2D input port?

Ask a question - edaboard.com

Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
RTV map EDAboard.com map News map EDAboard.eu map EDAboard.de map EDAboard.co.uk map Opony