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System design in FPGA

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Andy
Guest

Mon Feb 22, 2010 11:01 pm   



As you've probably guessed, there is no one "best way" to partition a
design.

A much under-used method (IMHO) is that of vhdl blocks. Blocks are
like entities/architectures, but you don't have to specify the ports.
You can specify signals and objects that are local to that block, and
not visible anywhere else, but objects declared outside the block are
visible inside it.

For instance, if I had a set of entities or processes that shared a
set of signals amongst themselves, but not anywhere else, I could use
a block to encapsulate those entities/processes along with their
locally interconnecting signals, yet not have the overhead of passing
external interfaces through yet another layer of ports.

Andy

jc
Guest

Tue Feb 23, 2010 3:47 pm   



Don't make the methodology of I/O and module partitioning any more
complicated than it needs to be. As several have mentioned, keeping it
simple goes a long way toward debugging your design faster and
allowing others to understand the code when it comes to future
enhancements, mods, bug fixes, etc. That being said, IMO records add a
level of complexity--albeit add some power at your disposal--that
isn't necessary for most of your simpler architectures. As far as
partitioning goes, I like to block out modules (or entities) into well-
defined functions, much like you would create one of your "blocks" in
a block diagram.

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