Synthesizable heap-sorter for FPGA - BSD licensed sources

Mon Jul 11, 2011 8:55 pm   

Hi,

I have prepared a heap-sorter implementation for FPGA. The sources are
licensed under the BSD license and
are available at alt.sources group.
Due to the fact, that I'm on my holidays, I was not able to post the
standard shar archive, and instead I have finally to send the
uuencoded tar.bz archive.
You can find it at: http://groups.google.com/group/alt.sources/msg/ab4bda56ca52cc59?dmode=source
(copy the body of the message to the file, then run "uudecode" on this
file, and you'll get sorter.tar.bz2 archive).

The sorter is able to sort one data record every 2 clock pulses.
I was able to compile into Virtex-6 XC6VLX75T-3FF484 a sorter with
capacity of 65535 records (able to sort the data stream with maximum
distance between unsorted records equal to 65535) with each record
containing 18 bits of time-stamp and 20 bits of payload.

More information is available at the beginning of my alt.sources post.
The current sources will be available (a little later) at
http://www.ise.pw.edu.pl/~wzab/fpga_heapsort
--
HTH & Best regards,
Wojtek Zabolotny

Fri Oct 14, 2011 3:10 pm   

Hi,

The article describing my "Synthesizable heap-sorter for FPGA"
(available at http://www.ise.pw.edu.pl/~wzab/fpga_heapsort)
is just published and available at http://dx.doi.org/10.1117/12.905281

--
Regards, Wojtek