KaRtiK
Guest
Fri Jan 30, 2004 11:11 pm
Hello
Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?
I want to compare layouts of different designs and study the tool(Cadence).
Thanks
Kartik
www.cae.wisc.edu/~kartik
Jerry
Guest
Sat Jan 31, 2004 3:16 am
"KaRtiK" <kkrishnan_at_wisc.edu> wrote in message
news:11510c1b.0401301311.3ca40b32_at_posting.google.com...
Quote:
Hello
Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?
I want to compare layouts of different designs and study the
tool(Cadence).
Thanks
Kartik
www.cae.wisc.edu/~kartik
I thought Magma had a tool for this. RTL to GDSII
Cherrs
Jer
Z
Guest
Fri Feb 06, 2004 9:20 pm
What tool set u have? Depending on that I can tell u how to do this.
-zk
"Jerry" <nospam_at_nowhere.com> wrote in message news:<101m0f23tpce1d0_at_corp.supernews.com>...
Quote:
"KaRtiK" <kkrishnan_at_wisc.edu> wrote in message
news:11510c1b.0401301311.3ca40b32_at_posting.google.com...
Hello
Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?
I want to compare layouts of different designs and study the
tool(Cadence).
Thanks
Kartik
www.cae.wisc.edu/~kartik
I thought Magma had a tool for this. RTL to GDSII
Cherrs
Jer
KaRtiK
Guest
Sun Feb 08, 2004 11:49 pm
Hello
I have the entire setup of Cadence,Synopsys,Xilinx and Mentor Graphics
tools in my Research lab.
I have synthesized my code using Design compiler.and wondering what
would be the design flow if I need to generate a layout a Cadence.
Thanks
Kartik
www.cae.wisc.edu/~kartik
zpalak_at_yahoo.com (Z) wrote in message news:<ede4169e.0402061120.4a06ffd3_at_posting.google.com>...
Quote:
What tool set u have? Depending on that I can tell u how to do this.
-zk
"Jerry" <nospam_at_nowhere.com> wrote in message news:<101m0f23tpce1d0_at_corp.supernews.com>...
"KaRtiK" <kkrishnan_at_wisc.edu> wrote in message
news:11510c1b.0401301311.3ca40b32_at_posting.google.com...
Hello
Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?
I want to compare layouts of different designs and study the
tool(Cadence).
Thanks
Kartik
www.cae.wisc.edu/~kartik
I thought Magma had a tool for this. RTL to GDSII
Cherrs
Jer
Eyck Jentzsch
Guest
Mon Feb 09, 2004 1:53 pm
Give SiliconEnsemble a try
-Eyck
