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elektroda.net NewsGroups Forum Index - Synthesis

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Automatic Schematic Generation (System Graph) and Viewer Alfonso Acosta3 / 1439Mon Jul 23, 2007 3:59 pm Shannon
SynaptiCAD AllProducts, Synopsys, new programs, ola71 / 1117Fri Jul 20, 2007 12:52 pm Jogi
gate sizing and interconnect delay mahalingamv@gmail.com2 / 934Tue Jun 26, 2007 3:13 am mahalingamv@gmail.com
PrimePower Koustav4 / 1289Wed Jun 20, 2007 12:31 am Alvin Andries
[DC] Determine parameter in set_input_delay? Davy1 / 1129Mon Feb 26, 2007 11:46 pm Alvin Andries
Should I use an external synthesis tool? avishay1 / 734Sat Dec 30, 2006 9:44 am Gupta
error help highbluff2 / 1113Wed Nov 15, 2006 1:38 am Guest
create_generated_clock (syntax, do I need it?) Guest1 / 2024Mon Jul 31, 2006 10:38 pm are.aarseth@gmail.com
Single bit wires instead of [0:0] busses? stefimkert1 / 792Wed Jul 26, 2006 5:27 pm Alvin Andries
help me salu2 / 964Thu Jul 20, 2006 4:15 pm sspreddy@gmail.com
Design Compiler: Output mux for testing fails timing. Guest4 / 996Mon Jul 10, 2006 3:55 pm Guest
[synopsys] struggling stefimke3 / 1823Wed Jun 21, 2006 6:01 am stefimke
Too big load in netlist after DC synthesis gongguowang@yahoo.com2 / 866Thu Jun 15, 2006 9:36 am Aditya Ramachandran
Unsupported verilog construct with synopsys DC? Fazela1 / 861Thu Jun 15, 2006 8:56 am michaelst@gmail.com
dc_shell and disabling datapath optimization variable Fazela1 / 964Sun May 21, 2006 8:34 am michaelst@gmail.com
set_load & set_fanout_out skyworld1 / 957Thu May 18, 2006 8:38 am michaelst@gmail.com
Where can I find latency of my circuit in Synopsys Tools friend.05@gmail.com2 / 806Tue May 16, 2006 12:37 am SS
Pros/Cons of skew & latency? gopal2 / 934Fri May 12, 2006 6:49 am eda_cadence
synopsys parallel case Maryam4 / 1259Thu Apr 27, 2006 5:51 pm Michael Laajanen
design compiler help mahalingamv@gmail.com4 / 1055Wed Apr 12, 2006 11:51 pm tellankush@gmail.com
Nanosim with Synthesized Verilog Sibi1 / 982Tue Apr 11, 2006 4:45 pm m
problem with post synthesis simulation with Scirocco using s Fazela1 / 691Mon Apr 10, 2006 6:49 am battlefield2001
Infer dual-clock block RAM for Xilinx Amal1 / 961Fri Apr 07, 2006 3:55 pm John_H
Logic Depth Dependent Synthesis Guest1 / 774Thu Apr 06, 2006 11:40 pm David Wallace
Urgent Help for xilinx Synthesizing Guest4 / 790Mon Mar 27, 2006 10:12 pm Guest
Cell Layout View: Which Synopsys Tool? Guest2 / 786Mon Mar 27, 2006 5:35 pm Guest
Some questions about Synopsys Physical Compiler.. LOGICAL2 / 720Thu Mar 09, 2006 9:16 am michaelst@gmail.com
From which memory-deep it is more meaningfully to use a RAM calzinide1 / 730Wed Mar 08, 2006 9:25 am michaelst@gmail.com
Using a new standard cell library with Synopsys Design Analy Fazela1 / 813Thu Feb 16, 2006 12:08 pm Ashutosh
Latest CAD forums messages on your desktop Guest1 / 878Mon Jan 23, 2006 4:53 am cadsxxx
Close Timing and STA Anand P. Paralkar5 / 1012Mon Jan 09, 2006 4:23 am Guest
How to judge a complete verification Andy4 / 1012Fri Dec 23, 2005 4:23 am Guest
problems when using Formality Andy1 / 956Wed Dec 21, 2005 4:38 pm Guest
Looking for free Formality guide Andy1 / 784Mon Dec 19, 2005 8:10 pm Alvin Andries
LSI RAPIDCHIP Jerry2 / 1022Sun Dec 11, 2005 12:33 am Jerry
Unable to write edif files anup2 / 1003Thu Aug 25, 2005 5:36 am anup
Help on Gate count for the gated clock logic kumar1 / 915Tue Apr 05, 2005 3:10 am James Lu
LEF syntax description 192.115.106.272 / 2109Tue Apr 05, 2005 3:06 am James Lu
AWARITH usage ? m1 / 982Thu Jun 30, 2005 10:12 pm Alvin Andries
!! DOWNLOAD THE MOST POPULAR 2005's CRACKED SOFTWARE !! CrackSoft1 / 1579Sat Feb 26, 2005 9:54 am bernina
How to start with development for eda tools kevin1 / 908Sun Dec 05, 2004 1:47 am Tb_
Available: Open Source VHDL parser - for free server7 / 1066Thu Sep 23, 2004 11:47 am Larry Horse
Back Annotation simulations rajan2 / 853Sun Aug 08, 2004 3:12 pm rajan
Arnold Schwarzenegger Commits Suicide Guest1 / 806Sat Jul 24, 2004 2:48 pm Sporkman
ASIC RTL and FPGA RTL Anand P Paralkar1 / 997Mon Apr 26, 2004 12:09 pm Alexander Gnusin
error about synthesis and placement Nilesh1 / 828Fri Apr 23, 2004 3:30 am ka
Wire Load Models Anand P. Paralkar4 / 1365Fri Apr 23, 2004 3:28 am ka
When You Hear The Heavy Accent & The Poor Phone Connection.. Guest7 / 1129Thu Apr 08, 2004 8:53 pm Jeff Mowry
Help: Why synthesis tool can not synthesis this logic??? chip algernon2 / 802Fri Mar 19, 2004 7:10 pm Amit Gupta
Xst:528 - Multi-source in Unit>>Can any experienced experts Kirstie Wong1 / 1747Thu Mar 18, 2004 6:22 am Eyck Jentzsch

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elektroda.net NewsGroups Forum Index - Synthesis

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