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elektroda.net NewsGroups Forum Index - Synthesis
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| gate sizing and interconnect delay | mahalingamv@gmail.com | 2 / 395 | Tue Jun 26, 2007 3:13 am mahalingamv@gmail.com |
| PrimePower | Koustav | 4 / 447 | Wed Jun 20, 2007 12:31 am Alvin Andries |
| [DC] Determine parameter in set_input_delay? | Davy | 1 / 537 | Mon Feb 26, 2007 11:46 pm Alvin Andries |
| Should I use an external synthesis tool? | avishay | 1 / 309 | Sat Dec 30, 2006 9:44 am Gupta |
| error help | highbluff | 2 / 433 | Wed Nov 15, 2006 1:38 am Guest |
| Calculate Delay from .Lib file | Ali Arabi | 1 / 534 | Wed Aug 30, 2006 4:17 am mk |
| create_generated_clock (syntax, do I need it?) | Guest | 1 / 496 | Mon Jul 31, 2006 10:38 pm are.aarseth@gmail.com |
| Single bit wires instead of [0:0] busses? | stefimkert | 1 / 348 | Wed Jul 26, 2006 5:27 pm Alvin Andries |
| help me | salu | 2 / 429 | Thu Jul 20, 2006 4:15 pm sspreddy@gmail.com |
| Design Compiler: Output mux for testing fails timing. | Guest | 4 / 364 | Mon Jul 10, 2006 3:55 pm Guest |
| [synopsys] struggling | stefimke | 3 / 777 | Wed Jun 21, 2006 6:01 am stefimke |
| Too big load in netlist after DC synthesis | gongguowang@yahoo.com | 2 / 331 | Thu Jun 15, 2006 9:36 am Aditya Ramachandran |
| Unsupported verilog construct with synopsys DC? | Fazela | 1 / 330 | Thu Jun 15, 2006 8:56 am michaelst@gmail.com |
| dc_shell and disabling datapath optimization variable | Fazela | 1 / 342 | Sun May 21, 2006 8:34 am michaelst@gmail.com |
| set_load & set_fanout_out | skyworld | 1 / 344 | Thu May 18, 2006 8:38 am michaelst@gmail.com |
| Where can I find latency of my circuit in Synopsys Tools | friend.05@gmail.com | 2 / 296 | Tue May 16, 2006 12:37 am SS |
| Pros/Cons of skew & latency? | gopal | 2 / 377 | Fri May 12, 2006 6:49 am eda_cadence |
| synopsys parallel case | Maryam | 4 / 485 | Thu Apr 27, 2006 5:51 pm Michael Laajanen |
| design compiler help | mahalingamv@gmail.com | 4 / 404 | Wed Apr 12, 2006 11:51 pm tellankush@gmail.com |
| Nanosim with Synthesized Verilog | Sibi | 1 / 417 | Tue Apr 11, 2006 4:45 pm m |
| problem with post synthesis simulation with Scirocco using s | Fazela | 1 / 295 | Mon Apr 10, 2006 6:49 am battlefield2001 |
| Infer dual-clock block RAM for Xilinx | Amal | 1 / 392 | Fri Apr 07, 2006 3:55 pm John_H |
| Logic Depth Dependent Synthesis | Guest | 1 / 315 | Thu Apr 06, 2006 11:40 pm David Wallace |
| Urgent Help for xilinx Synthesizing | Guest | 4 / 373 | Mon Mar 27, 2006 10:12 pm Guest |
| Cell Layout View: Which Synopsys Tool? | Guest | 2 / 321 | Mon Mar 27, 2006 5:35 pm Guest |
| Some questions about Synopsys Physical Compiler.. | LOGICAL | 2 / 288 | Thu Mar 09, 2006 9:16 am michaelst@gmail.com |
| From which memory-deep it is more meaningfully to use a RAM | calzinide | 1 / 291 | Wed Mar 08, 2006 9:25 am michaelst@gmail.com |
| Using a new standard cell library with Synopsys Design Analy | Fazela | 1 / 369 | Thu Feb 16, 2006 12:08 pm Ashutosh |
| Latest CAD forums messages on your desktop | Guest | 1 / 332 | Mon Jan 23, 2006 4:53 am cadsxxx |
| Close Timing and STA | Anand P. Paralkar | 5 / 410 | Mon Jan 09, 2006 4:23 am Guest |
| How to judge a complete verification | Andy | 4 / 365 | Fri Dec 23, 2005 4:23 am Guest |
| problems when using Formality | Andy | 1 / 332 | Wed Dec 21, 2005 4:38 pm Guest |
| Looking for free Formality guide | Andy | 1 / 309 | Mon Dec 19, 2005 8:10 pm Alvin Andries |
| LSI RAPIDCHIP | Jerry | 2 / 484 | Sun Dec 11, 2005 12:33 am Jerry |
| Unable to write edif files | anup | 2 / 467 | Thu Aug 25, 2005 5:36 am anup |
| Help on Gate count for the gated clock logic | kumar | 1 / 472 | Tue Apr 05, 2005 3:10 am James Lu |
| LEF syntax description | 192.115.106.27 | 2 / 994 | Tue Apr 05, 2005 3:06 am James Lu |
| AWARITH usage ? | m | 1 / 461 | Thu Jun 30, 2005 10:12 pm Alvin Andries |
| !! DOWNLOAD THE MOST POPULAR 2005's CRACKED SOFTWARE !! | CrackSoft | 1 / 779 | Sat Feb 26, 2005 9:54 am bernina |
| How to start with development for eda tools | kevin | 1 / 473 | Sun Dec 05, 2004 1:47 am Tb_ |
| Available: Open Source VHDL parser - for free | server | 7 / 495 | Thu Sep 23, 2004 11:47 am Larry Horse |
| Back Annotation simulations | rajan | 2 / 399 | Sun Aug 08, 2004 3:12 pm rajan |
| Arnold Schwarzenegger Commits Suicide | Guest | 1 / 348 | Sat Jul 24, 2004 2:48 pm Sporkman |
| ASIC RTL and FPGA RTL | Anand P Paralkar | 1 / 406 | Mon Apr 26, 2004 12:09 pm Alexander Gnusin |
| error about synthesis and placement | Nilesh | 1 / 401 | Fri Apr 23, 2004 3:30 am ka |
| Wire Load Models | Anand P. Paralkar | 4 / 667 | Fri Apr 23, 2004 3:28 am ka |
| When You Hear The Heavy Accent & The Poor Phone Connection.. | Guest | 7 / 500 | Thu Apr 08, 2004 8:53 pm Jeff Mowry |
| Help: Why synthesis tool can not synthesis this logic??? | chip algernon | 2 / 374 | Fri Mar 19, 2004 7:10 pm Amit Gupta |
| Xst:528 - Multi-source in Unit>>Can any experienced experts | Kirstie Wong | 1 / 595 | Thu Mar 18, 2004 6:22 am Eyck Jentzsch |
| Synopsys .lib/.tlf to .db conversion | P. Kumar | 1 / 564 | Mon Mar 08, 2004 7:35 am Ansgar Bambynek |
elektroda.net NewsGroups Forum Index - Synthesis