EDAboard.com | EDAboard.eu | EDAboard.de | EDAboard.co.uk | RTV forum PL | NewsGroups PL

elektroda.net NewsGroups Forum Index - Synthesis - **Synthesis errors?**

Guest

Thu Jan 22, 2004 12:51 am

Hi,

I have recently had lots of incorrectly synthesised logic with the

synthesiser I am using.

My latest design occupied approx 20% of a "6 million gate" FPGA, and had a

total of 5

incorrectly synthesised parts (which took some finding).

Can anyone recommend any synthesisers which do not suffer from this sort of

problem?

The synth takes approx 1 hour to synth this (much quicker than most of my

"large" designs), and timing far

exceeds the requirements as the clock frequency is low.

If anyone is interested, the sort of errors I was getting were:-

A connection between 2 components was simply not made. An input to the

second component was hardwired to '0'.

Tried the very latest version of the same synth and the problem went away.

The following problems were seen in the latest version:-

OUT_DATA <= IN_DATA & "0";

synthesised to

OUT_DATA <= "0" & IN_DATA;

put this in a clocked process and it synthesised correctly.

OUT_DATA <= 2**IN_DATA;

had OUT_DATA(0) hardwired to '1'.

replaced with a case statement and it synthesised correctly

if X = -1 then

OUT_DATA <= IN_DATA;

elsif X= 1 then

OUT_DATA <= 0 - IN_DATA;

elsif X=0 then

OUT_DATA <= 0;

else

OUT_DATA <= 0 - IN_DATA;

end if;

had OUT_DATA=0 when X=-1

put calculation of 0 - IN_DATA in a separate clocked process, and it

synthesised correctly.

An inferred ROM which synthesised correctly in an earlier version of the

synthesiser, now infers a ROM filled with zeros.

I worked around this by adding a reset to cause the ROM function to be built

from logic. This greatly increased

the size, but this is not a problem for the particular design.

I tried synthing the rogue pieces of code standalone, and they were synthed

correctly (apart from the ROM).

Thanks,

Ken,

Morrow Electronics Limited,

Milton Keynes,

UK.

kenm_at_morro.co.uk without the m after my name otherwise it will not be

delivered.

Guest

Thu Jan 22, 2004 5:12 am

The Quartus II 3.0 Tool from Altera has a good VHDL/Verilog parser and

synthesis capability. The output of the synthesiser will work only with the

place and route tools from Altera, and you target all of the Altera devices.

A free version of the tools is available from:

https://www.altera.com/support/software/download/altera_design/quartus_we/dn

l-quartus_we.jsp

- Subroto Datta

Altera Corp.

"Ken Morrow" <junk_at_not_morro.co.uk> wrote in message

news:wmDPb.26583$qx2.3022656_at_stones.force9.net...

Hi,

I have recently had lots of incorrectly synthesised logic with the

synthesiser I am using.

My latest design occupied approx 20% of a "6 million gate" FPGA, and had a

total of 5

incorrectly synthesised parts (which took some finding).

Can anyone recommend any synthesisers which do not suffer from this sort

of

problem?

The synth takes approx 1 hour to synth this (much quicker than most of my

"large" designs), and timing far

exceeds the requirements as the clock frequency is low.

If anyone is interested, the sort of errors I was getting were:-

A connection between 2 components was simply not made. An input to the

second component was hardwired to '0'.

Tried the very latest version of the same synth and the problem went away.

The following problems were seen in the latest version:-

OUT_DATA <= IN_DATA & "0";

synthesised to

OUT_DATA <= "0" & IN_DATA;

put this in a clocked process and it synthesised correctly.

OUT_DATA <= 2**IN_DATA;

had OUT_DATA(0) hardwired to '1'.

replaced with a case statement and it synthesised correctly

if X = -1 then

OUT_DATA <= IN_DATA;

elsif X= 1 then

OUT_DATA <= 0 - IN_DATA;

elsif X=0 then

OUT_DATA <= 0;

else

OUT_DATA <= 0 - IN_DATA;

end if;

had OUT_DATA=0 when X=-1

put calculation of 0 - IN_DATA in a separate clocked process, and it

synthesised correctly.

An inferred ROM which synthesised correctly in an earlier version of the

synthesiser, now infers a ROM filled with zeros.

I worked around this by adding a reset to cause the ROM function to be

built

from logic. This greatly increased

the size, but this is not a problem for the particular design.

I tried synthing the rogue pieces of code standalone, and they were

synthed

correctly (apart from the ROM).

Thanks,

Ken,

Morrow Electronics Limited,

Milton Keynes,

UK.

kenm_at_morro.co.uk without the m after my name otherwise it will not be

delivered.

I have recently had lots of incorrectly synthesised logic with the

synthesiser I am using.

My latest design occupied approx 20% of a "6 million gate" FPGA, and had a

total of 5

incorrectly synthesised parts (which took some finding).

Can anyone recommend any synthesisers which do not suffer from this sort

of

problem?

The synth takes approx 1 hour to synth this (much quicker than most of my

"large" designs), and timing far

exceeds the requirements as the clock frequency is low.

If anyone is interested, the sort of errors I was getting were:-

A connection between 2 components was simply not made. An input to the

second component was hardwired to '0'.

Tried the very latest version of the same synth and the problem went away.

The following problems were seen in the latest version:-

OUT_DATA <= IN_DATA & "0";

synthesised to

OUT_DATA <= "0" & IN_DATA;

put this in a clocked process and it synthesised correctly.

OUT_DATA <= 2**IN_DATA;

had OUT_DATA(0) hardwired to '1'.

replaced with a case statement and it synthesised correctly

if X = -1 then

OUT_DATA <= IN_DATA;

elsif X= 1 then

OUT_DATA <= 0 - IN_DATA;

elsif X=0 then

OUT_DATA <= 0;

else

OUT_DATA <= 0 - IN_DATA;

end if;

had OUT_DATA=0 when X=-1

put calculation of 0 - IN_DATA in a separate clocked process, and it

synthesised correctly.

An inferred ROM which synthesised correctly in an earlier version of the

synthesiser, now infers a ROM filled with zeros.

I worked around this by adding a reset to cause the ROM function to be

built

from logic. This greatly increased

the size, but this is not a problem for the particular design.

I tried synthing the rogue pieces of code standalone, and they were

synthed

correctly (apart from the ROM).

Thanks,

Ken,

Morrow Electronics Limited,

Milton Keynes,

UK.

kenm_at_morro.co.uk without the m after my name otherwise it will not be

delivered.

Guest

Thu Jan 22, 2004 8:38 am

Ken Morrow wrote:

Hi,

I have recently had lots of incorrectly synthesised logic with the

synthesiser I am using.

My latest design occupied approx 20% of a "6 million gate" FPGA, and had a

total of 5

incorrectly synthesised parts (which took some finding).

Can anyone recommend any synthesisers which do not suffer from this sort of

problem?

The synth takes approx 1 hour to synth this (much quicker than most of my

"large" designs), and timing far

exceeds the requirements as the clock frequency is low.

If anyone is interested, the sort of errors I was getting were:-

A connection between 2 components was simply not made. An input to the

second component was hardwired to '0'.

Tried the very latest version of the same synth and the problem went away.

The following problems were seen in the latest version:-

OUT_DATA <= IN_DATA & "0";

synthesised to

OUT_DATA <= "0" & IN_DATA;

put this in a clocked process and it synthesised correctly.

OUT_DATA <= 2**IN_DATA;

had OUT_DATA(0) hardwired to '1'.

replaced with a case statement and it synthesised correctly

if X = -1 then

OUT_DATA <= IN_DATA;

elsif X= 1 then

OUT_DATA <= 0 - IN_DATA;

elsif X=0 then

OUT_DATA <= 0;

else

OUT_DATA <= 0 - IN_DATA;

end if;

had OUT_DATA=0 when X=-1

put calculation of 0 - IN_DATA in a separate clocked process, and it

synthesised correctly.

An inferred ROM which synthesised correctly in an earlier version of the

synthesiser, now infers a ROM filled with zeros.

I worked around this by adding a reset to cause the ROM function to be built

from logic. This greatly increased

the size, but this is not a problem for the particular design.

I tried synthing the rogue pieces of code standalone, and they were synthed

correctly (apart from the ROM).

Thanks,

Ken,

Morrow Electronics Limited,

Milton Keynes,

UK.

kenm_at_morro.co.uk without the m after my name otherwise it will not be

delivered.

I have recently had lots of incorrectly synthesised logic with the

synthesiser I am using.

My latest design occupied approx 20% of a "6 million gate" FPGA, and had a

total of 5

incorrectly synthesised parts (which took some finding).

Can anyone recommend any synthesisers which do not suffer from this sort of

problem?

The synth takes approx 1 hour to synth this (much quicker than most of my

"large" designs), and timing far

exceeds the requirements as the clock frequency is low.

If anyone is interested, the sort of errors I was getting were:-

A connection between 2 components was simply not made. An input to the

second component was hardwired to '0'.

Tried the very latest version of the same synth and the problem went away.

The following problems were seen in the latest version:-

OUT_DATA <= IN_DATA & "0";

synthesised to

OUT_DATA <= "0" & IN_DATA;

put this in a clocked process and it synthesised correctly.

OUT_DATA <= 2**IN_DATA;

had OUT_DATA(0) hardwired to '1'.

replaced with a case statement and it synthesised correctly

if X = -1 then

OUT_DATA <= IN_DATA;

elsif X= 1 then

OUT_DATA <= 0 - IN_DATA;

elsif X=0 then

OUT_DATA <= 0;

else

OUT_DATA <= 0 - IN_DATA;

end if;

had OUT_DATA=0 when X=-1

put calculation of 0 - IN_DATA in a separate clocked process, and it

synthesised correctly.

An inferred ROM which synthesised correctly in an earlier version of the

synthesiser, now infers a ROM filled with zeros.

I worked around this by adding a reset to cause the ROM function to be built

from logic. This greatly increased

the size, but this is not a problem for the particular design.

I tried synthing the rogue pieces of code standalone, and they were synthed

correctly (apart from the ROM).

Thanks,

Ken,

Morrow Electronics Limited,

Milton Keynes,

UK.

kenm_at_morro.co.uk without the m after my name otherwise it will not be

delivered.

Every synthesizer will suffer 'cause all of them are SW and SW (as well

as HW has bugs... The only solution to that problem would be to use

an equivalence checker to check the generated Netlist against the RTL.

They are also not bug free, but if the do not share code, the

probability of having the same bug is near to 0. Tools in that area are

for example Verplex LEC but there are a lot more.

HTH

-Eyck

Guest

Thu Jan 22, 2004 2:57 pm

I have used a lot of the synthesisers out there and I have had errors with

all of them at one time or another. I have usually tackled them in the way

you describe. Usually I have found particular constructs to be the issue and

generally avoid the ones that cause problems. Generally the best way to find

the bugs is in a post synthesis simulation. Do this ideally with a self

checking testbench that you can run on a spare machine in the background. It

can be a long process on a big design.

To reduce the long synthesis/simulation times consider using modular

synthesis and simulation. Some tools will do this automatically for you.

Using this approach you can virtually ignore "good" modules and look for

problems in the modules you have actually changed either by design or

synthesis. I hope to have a article on the cheap and cheerful approach to

this in our TechiTips page either this month or next.

John Adair

Enterpoint Ltd.

This message is the personal opinion of the sender and not that necessarily

that of Enterpoint Ltd.. Readers should make their own evaluation of the

facts. No responsibility for error or inaccuracy is accepted.

"Ken Morrow" <junk_at_not_morro.co.uk> wrote in message

news:wmDPb.26583$qx2.3022656_at_stones.force9.net...

Hi,

I have recently had lots of incorrectly synthesised logic with the

synthesiser I am using.

My latest design occupied approx 20% of a "6 million gate" FPGA, and had a

total of 5

incorrectly synthesised parts (which took some finding).

Can anyone recommend any synthesisers which do not suffer from this sort

of

problem?

The synth takes approx 1 hour to synth this (much quicker than most of my

"large" designs), and timing far

exceeds the requirements as the clock frequency is low.

If anyone is interested, the sort of errors I was getting were:-

A connection between 2 components was simply not made. An input to the

second component was hardwired to '0'.

Tried the very latest version of the same synth and the problem went away.

The following problems were seen in the latest version:-

OUT_DATA <= IN_DATA & "0";

synthesised to

OUT_DATA <= "0" & IN_DATA;

put this in a clocked process and it synthesised correctly.

OUT_DATA <= 2**IN_DATA;

had OUT_DATA(0) hardwired to '1'.

replaced with a case statement and it synthesised correctly

if X = -1 then

OUT_DATA <= IN_DATA;

elsif X= 1 then

OUT_DATA <= 0 - IN_DATA;

elsif X=0 then

OUT_DATA <= 0;

else

OUT_DATA <= 0 - IN_DATA;

end if;

had OUT_DATA=0 when X=-1

put calculation of 0 - IN_DATA in a separate clocked process, and it

synthesised correctly.

An inferred ROM which synthesised correctly in an earlier version of the

synthesiser, now infers a ROM filled with zeros.

I worked around this by adding a reset to cause the ROM function to be

built

from logic. This greatly increased

the size, but this is not a problem for the particular design.

I tried synthing the rogue pieces of code standalone, and they were

synthed

correctly (apart from the ROM).

Thanks,

Ken,

Morrow Electronics Limited,

Milton Keynes,

UK.

kenm_at_morro.co.uk without the m after my name otherwise it will not be

delivered.

I have recently had lots of incorrectly synthesised logic with the

synthesiser I am using.

My latest design occupied approx 20% of a "6 million gate" FPGA, and had a

total of 5

incorrectly synthesised parts (which took some finding).

Can anyone recommend any synthesisers which do not suffer from this sort

of

problem?

The synth takes approx 1 hour to synth this (much quicker than most of my

"large" designs), and timing far

exceeds the requirements as the clock frequency is low.

If anyone is interested, the sort of errors I was getting were:-

A connection between 2 components was simply not made. An input to the

second component was hardwired to '0'.

Tried the very latest version of the same synth and the problem went away.

The following problems were seen in the latest version:-

OUT_DATA <= IN_DATA & "0";

synthesised to

OUT_DATA <= "0" & IN_DATA;

put this in a clocked process and it synthesised correctly.

OUT_DATA <= 2**IN_DATA;

had OUT_DATA(0) hardwired to '1'.

replaced with a case statement and it synthesised correctly

if X = -1 then

OUT_DATA <= IN_DATA;

elsif X= 1 then

OUT_DATA <= 0 - IN_DATA;

elsif X=0 then

OUT_DATA <= 0;

else

OUT_DATA <= 0 - IN_DATA;

end if;

had OUT_DATA=0 when X=-1

put calculation of 0 - IN_DATA in a separate clocked process, and it

synthesised correctly.

An inferred ROM which synthesised correctly in an earlier version of the

synthesiser, now infers a ROM filled with zeros.

I worked around this by adding a reset to cause the ROM function to be

built

from logic. This greatly increased

the size, but this is not a problem for the particular design.

I tried synthing the rogue pieces of code standalone, and they were

synthed

correctly (apart from the ROM).

Thanks,

Ken,

Morrow Electronics Limited,

Milton Keynes,

UK.

kenm_at_morro.co.uk without the m after my name otherwise it will not be

delivered.

elektroda.net NewsGroups Forum Index - Synthesis - **Synthesis errors?**