Maryam
Guest
Sun Apr 16, 2006 4:24 am
Hi,
Would you mind please explain me the "synopsys parallel case " in
verilog.
Thanks a lot
Maryam
michaelst@gmail.com
Guest
Sun Apr 16, 2006 7:44 am
I means that synopsys will build parallel logic for your mux.
Maryam
Guest
Mon Apr 17, 2006 9:12 am
Thanks,
but please let me know it in details,what is the difference between the
synopsys parallel case and normal case?How and when we do use it?
If you can send me a link to read more about it I will be thankfull.
Maryam
m
Guest
Mon Apr 17, 2006 2:42 pm
On 17 Apr 2006 02:12:31 -0700, "Maryam" <maryam.darvishan_at_gmail.com>
wrote:
Quote:
Thanks,
but please let me know it in details,what is the difference between the
synopsys parallel case and normal case?How and when we do use it?
If you can send me a link to read more about it I will be thankfull.
Maryam
Google is your friend: try
http://www.google.com/search?hl=en&q=parallel+case+verilog&btnG=Google+Search.
The first three links are pretty good.
Michael Laajanen
Guest
Thu Apr 27, 2006 5:51 pm
Hi,
Maryam wrote:
Quote:
Thanks,
but please let me know it in details,what is the difference between the
synopsys parallel case and normal case?How and when we do use it?
If you can send me a link to read more about it I will be thankfull.
Maryam
Without "synopsys parallel case" the case will be similar like a "if
then elsif elsif" statement.
/michael
