Don Otknow
Guest
Fri Mar 04, 2011 9:40 pm
Hello,
I want to know if there is a way to group variables in VHDL that self-
documents better than an array and allows for different types (IE the
equivalent of a C struct). Is the record type this? Can one use
signals and variables inside a record, and can a single record have
both? Synthesis issues?
Thanks,
Don
Mike Treseler
Guest
Fri Mar 04, 2011 9:40 pm
On 3/4/2011 11:40 AM, Don Otknow wrote:
Quote:
I want to know if there is a way to group variables in VHDL that self-
documents better than an array and allows for different types (IE the
equivalent of a C struct). Is the record type this?
Yes, but not exactly.
Quote:
Can one use
signals and variables inside a record,
I can use a record variable inside a process or
I can use a record signal inside an architecture.
Quote:
and can a single record have
both?
No. A record is *type* of signal, variable or constant.
Synthesis issues?
These are minimized by avoiding record type ports.
Goggle comp.lang.vhdl. That subject has been beaten to death.
-- Mike Treseler
Tricky
Guest
Sat Mar 05, 2011 1:30 am
Quote:
Synthesis issues?
These are minimized by avoiding record type ports.
Goggle comp.lang.vhdl. That subject has been beaten to death.
-- Mike Treseler
Avoid record types for ports - since when? Maybe for inouts, but for
single direction they are handy.
Brian Drummond
Guest
Sat Mar 05, 2011 8:44 am
On Fri, 4 Mar 2011 15:30:51 -0800 (PST), Tricky <trickyhead_at_gmail.com> wrote:
Quote:
Synthesis issues?
These are minimized by avoiding record type ports.
Goggle comp.lang.vhdl. That subject has been beaten to death.
-- Mike Treseler
Avoid record types for ports - since when? Maybe for inouts, but for
single direction they are handy.
The problem with inout ports being that you cannot (currently) drive different
elements of the record in different directions. Which means you can't wrap
Address, Data, Read, Write, Ack into a record (dammit...)
Closest solution is two records : Address, Data_Out, Read, Write in one; Data_In
and Ack in the other. (Bidirectional buses are deprecated inside new FPGAs
anyway)
Also avoid them for external (off-chip) ports. Synthesis etc will convert all
off-chip signals to std_[u]_logic[_vector]. Which makes dropping the post-synth
netlist into your testbench a pain, unless you create a wrapper to convert port
types.
Other than these, I can't think of any synthesis issues.
- Brian
Thomas Stanka
Guest
Tue Mar 08, 2011 11:00 am
On 5 Mrz., 08:44, Brian Drummond <brian_drumm...@btconnect.com> wrote:
Quote:
Also avoid them for external (off-chip) ports. Synthesis etc will convert all
off-chip signals to std_[u]_logic[_vector]. Which makes dropping the post-synth
netlist into your testbench a pain, unless you create a wrapper to convert port
types.
Other than these, I can't think of any synthesis issues.
Synopsys DC converts all elements of the record into one array. No
problem for small records, but it makes design handling quite hard, if
your record is complex or nested and has some wide bus. I once had
seen a record as Input that results in an array of more than 100 bits
as Input after synthesis on top level of the design. Was no fun to
collect adress, data and control signals out of this bus.
bye Thomas
