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String list parser in VHDL...

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Guest

Sun Nov 20, 2016 9:05 pm   



I am designing a VHDL combinational block that takes in a list of 8
ASCII characters as input and replaces the non-numeral characters with a
dash '-', then rearranges the list to have the numerals on one side and
'-'s on the other.

Example input and output:

Input: d126r24! Output: ---12246

Source Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity module1 is
port (list1: IN string (1 to Cool;
list2: OUT string (1 to Cool);
end entity;

architecture behavior of module1 is
signal temp: string (1 to Cool;

begin

process (list1)
variable a: integer:= 1;
variable b: integer:= 8;
variable c: string (1 to Cool;
begin

for i in 1 to 8 loop
if ((list1(i) = '0') or (list1(i) = '1') or (list1(i) = '2') or (list1(i) = '3') or (list1(i) = '4') or (list1(i) = '5') or (list1(i) = '6') or (list1(i) = '7') or (list1(i) = '8') or (list1(i) = '9')) then
c(a):= list1(i);
a := a + 1;
else
c(b) := '-';
b := b - 1;
end if;
end loop;

temp <= c;
end process;
list2 <= temp;
end behavior;


TEST BENCH:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_module1 is
end entity;

architecture behavior of tb_module1 is
component module1
port (list1: IN string (1 to Cool;
list2: OUT string (1 to Cool);
end component;

signal list1, list2: string (1 to Cool;
begin
DUT: module1 port map (list1 => list1, list2 => list2);

process
begin
wait for 0 ns;
list1 <= "12345678";
wait for 10 ns;
list1 <= "001122nn";
wait for 10 ns;
end process;
end behavior;


ISSUE: codes compile fine but upon simulating I get a fatal error in modelsim:

"run
# ** Fatal: (vsim-3734) Index value 9 is out of range 1 to 8.
# Time: 10 ns Iteration: 1 Process: /tb_module1/DUT/line__15 File: C:/Modeltech_pe_edu_10.4a/examples/module1.vhd
# Fatal error in ForLoop loop at C:/Modeltech_pe_edu_10.4a/examples/module1.vhd line 23
#
# HDL call sequence:
# Stopped at C:/Modeltech_pe_edu_10.4a/examples/module1.vhd 23 ForLoop loop"

I cannot understand how this index error is happening. Please help!

Anssi Saari
Guest

Mon Nov 21, 2016 6:41 pm   



omarjamal77_at_gmail.com writes:

Quote:
ISSUE: codes compile fine but upon simulating I get a fatal error in modelsim:

"run
# ** Fatal: (vsim-3734) Index value 9 is out of range 1 to 8.


You need to reset the values of a and b after the loop, otherwise with
the second input they start from whatever values they ended up with on
the previous execution of the process. In your testcase, a is 8 when
processing the second input starts and so goes out of bounds as soon as
it's incremented.

Allan Herriman
Guest

Mon Nov 21, 2016 6:56 pm   



On Sun, 20 Nov 2016 11:05:10 -0800, omarjamal77 wrote:

Quote:
I am designing a VHDL combinational block that takes in a list of 8
ASCII characters as input and replaces the non-numeral characters with a
dash '-', then rearranges the list to have the numerals on one side and
'-'s on the other.

Example input and output:

Input: d126r24! Output: ---12246

Source Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity module1 is
port (list1: IN string (1 to Cool;
list2: OUT string (1 to Cool);
end entity;

architecture behavior of module1 is signal temp: string (1 to Cool;

begin

process (list1)
variable a: integer:= 1;
variable b: integer:= 8;
variable c: string (1 to Cool;
begin

for i in 1 to 8 loop
if ((list1(i) = '0') or (list1(i) = '1') or (list1(i) = '2') or
(list1(i) = '3') or (list1(i) = '4') or (list1(i) = '5') or (list1
(i) =
'6') or (list1(i) = '7') or (list1(i) = '8') or (list1(i) = '9'))
then
c(a):= list1(i);
a := a + 1;
else
c(b) := '-';
b := b - 1;
end if;
end loop;

temp <= c;
end process;
list2 <= temp;
end behavior;


TEST BENCH:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_module1 is end entity;

architecture behavior of tb_module1 is component module1
port (list1: IN string (1 to Cool;
list2: OUT string (1 to Cool);
end component;

signal list1, list2: string (1 to Cool;
begin DUT: module1 port map (list1 => list1, list2 => list2);

process begin wait for 0 ns;
list1 <= "12345678";
wait for 10 ns;
list1 <= "001122nn";
wait for 10 ns;
end process;
end behavior;


ISSUE: codes compile fine but upon simulating I get a fatal error in
modelsim:

"run # ** Fatal: (vsim-3734) Index value 9 is out of range 1 to 8.
# Time: 10 ns Iteration: 1 Process: /tb_module1/DUT/line__15 File:
C:/Modeltech_pe_edu_10.4a/examples/module1.vhd # Fatal error in ForLoop
loop at C:/Modeltech_pe_edu_10.4a/examples/module1.vhd line 23 #
# HDL call sequence:
# Stopped at C:/Modeltech_pe_edu_10.4a/examples/module1.vhd 23 ForLoop
loop"

I cannot understand how this index error is happening. Please help!


The loop iterator 'i' is always within the range 1 to 8, but the
variables 'a' and 'b' are not.

Hint: change their declaration from:

variable a: integer:= 1;
variable b: integer:= 8;

to

variable a: integer range 1 to 8 := 1;
variable b: integer range 1 to 8 := 8;

and you will see that this is true. Variable 'a' will overflow once your
code has processed more than 8 digits.


The basic problem is that the initialisers for variables 'a' and 'b' are
only done once at the start of simulation. They are not reinitialised
every time the process is run. (It's just how VHDL works.)

You can fix that by adding the following statements just before the for
loop.

a := 1;
b := 8;


Regards,
Allan

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