Stratix iv PLLs ref clock

Sat Aug 28, 2010 12:03 pm   

Hi All,

My design is meant to work at two speed modes(full & half rate).
Initially I used one clk source(560MHz) plus enable. However, I envisage
changing the plan to divide the clk itself from origin(instead of enable)
so that the design is simplified and becomes identical in both cases apart
from clk speed.

The problem is that I have to use an FPGA on-chip PLL, which expects an
input clk of 560MHz but will receive either 560 MHz in full mode or 280MHz
in division mode. The PLL seem to lock in both cases.

Does anybody foresee PLL problems in this approach or what else can be done
to keep PLL design as recommended by Altera. Knowing that I can't switch
between two PLLs.

Regards

Kadheim

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Sat Aug 28, 2010 12:17 pm   

kadhiem_ayob wrote:


I don't know, if it helps for your problem, but you can switch between two
PLLs, at least I've used this for a Cyclone chip, so should be possible
with Stratix, too. Open Megawizard and choose altclkctrl in the I/O folder.
You can input customize it for two clocks and there is a checkbox for
glitch-free switchover. Works nice in one of my designs.

Another idea would be to use altpll_reconfig, but I don't have experience
with it.

--
Frank Buss, http://www.frank-buss.de
piano and more: http://www.youtube.com/user/frankbuss

Sat Aug 28, 2010 12:34 pm   

Thanks Frank

However, I only have one physical clk input which carries clk signal a
either 560 or 280Mhz to same PLL.

One option may be to use two PLLs set one at 560 and one at 280 inputs fe
by same input then mux out the outputs but I know this approach is risky a
both the PLL's input side and its output side.
I prefer to have one PLL and enter ref clk as 560 then "cheat" the PLL an
inject 280MHz in half mode. It locks and seems happy. But I am not sure i
the design will be reliable and acceptable "legally".

Regards

Kadhiem

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Sat Aug 28, 2010 9:09 pm   

On Aug 28, 1:34 pm, "kadhiem_ayob"
<kadhiem_ayob_at_n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:

Look at QuartusII fitter report under PLL usage tab or something
similar. They report max and min lock frequency for the reference
clock. If you see that you are far off then try to play with reference
clock frequency and bandwidth settings in megawithard. If it still
doesn't help then the only safe option is reconfiguring the PLL on the
fly. That's of course will only work when you have some other "safe"
clock for reconfiguration.
But then again if you have the safe clock may be it's a good idea to
use it and possibly its derivate throughout your FPGA design instead
of 280/560 clock? I am assuming that 280/560 clock comes from external
PLL and drives some ADC or DAC and you can't use Stratix PLL for that
because its jitter sucks. However it's normally very good idea to use
that DAC/ADC clock in FPGA only to drive ADC/DAC samples into/out of
small FIFO and base the rest of design on the other "safe" internally
generated clock.