std_logic_vector to integer

Fri May 27, 2011 2:53 am   

Hi!

I'm beginner. I can't solve this problem. I'm trying to convert
std_logic_vector to integer.

It doesn't work. I have an error:
line 215: Different types for port <o> on entity and component for
<VectorToInteger>

------------
-- Code:


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;

entity VectorToInteger is port (
Clk_50MHz: in std_logic;
i: in std_logic_vector(7 downto 0);
o: out Integer range 300 downto -127);
end VectorToInteger;

architecture Behavioral of VectorToInteger is
begin
process(Clk_50MHz, i)
begin
if (rising_edge(Clk_50MHz)) then
o <= conv_integer(i);
end if;
end process;
end Behavioral;

-----------------


This is very important for me. Please help me...
Piotr

Fri May 27, 2011 5:07 am   

"Piotr" <brak_at_brak.pl> wrote in message
news:4ddf1231$0$2456$65785112_at_news.neostrada.pl...

Do not use std_logic_arith and std_logic_signed. Use numeric_std instead.
You will find all the required functions there

Fri May 27, 2011 6:17 am   

Thank You very much. I've solved the problem.

Piotr

Fri May 27, 2011 7:30 am   

On 27 Mai, 07:07, "scrts" <hid...@email.com> wrote:

numeric_std, you might find this
http://www.lothar-miller.de/s9y/uploads/Bilder/Usage_of_numeric_std.pdf
helpfull.

Greetings from rainy Bremen,

hhanff