State machines in Quartus

Sun Feb 21, 2010 6:34 am   

I'm trying to get Quartus to recognize my state machines. I'm
using version 9.0. I tried generating a state machine using the
State Machine Wizard, but after compiling, if I try to look at it
with the State Machine Viewer I get "This design has no State
Machine." I tried to copy the Verilog code from the Help file,
and I still get the same problem.

Is it possible to get Quartus to understand my state machines?

Sun Feb 21, 2010 6:06 pm   

Giorgos Tzampanakis wrote:

I would look at the RTL view to
see how the code synthesized.


Yes. The Quartus viewer draws a state diagram when
I update an enumeration using a case statement.
Learn vhdl or verilog and get a simulator.

-- Mike Treseler

Sun Feb 21, 2010 10:57 pm   

On Feb 20, 11:34 pm, Giorgos Tzampanakis <g...@hw.ac.uk> wrote:

Without seeing the code I'm guessing it was optimized out. Quartus
defaults to one-hot state machines. In settings (someplace) you need
to tell it 'custom' or 'user defined' (I forget which). That might not
be enough, you might also have to associate each state with an output
signal or it might go poof. For small state machines I'll create a
signal and tie it to a pin with an LED.