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elektroda.net NewsGroups Forum Index - VHDL Language - **Squaring of a binary number**

Guest

Fri Jul 19, 2013 7:27 pm

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0 " ( a 10 bit number)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for the adding to get the final result).

Could anyone please help me out how to make a generalized code for squaring of a 5-bit number to get an output like this?

Many Thanks!

Guest

Fri Jul 19, 2013 8:38 pm

You might want to check your math! 11111 * 11111 = 1111000001.

Assuming use of proper types from numeric_std, try this:

result <= a * a;

Here is an excellent reference for VHDL math: http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

Guest

Fri Jul 19, 2013 9:08 pm

On Saturday, July 20, 2013 12:08:59 AM UTC+5:30, 1999o...@gmail.com wrote:

You might want to check your math! 11111 * 11111 = 1111000001.

Assuming use of proper types from numeric_std, try this:

result <= a * a;

Here is an excellent reference for VHDL math: http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

Assuming use of proper types from numeric_std, try this:

result <= a * a;

Here is an excellent reference for VHDL math: http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

Do not consider a simple binary addition. It is an XOR operation. You did the simple binary operation to get the result. But if you do XOR operation to add then you will get the same result as mine.

Guest

Fri Jul 19, 2013 9:15 pm

Le 19/07/2013 21:08, lokesh kumar a écrit :

Do not consider a simple binary addition. It is an XOR operation.

You did the simple binary operation to get the result. But if you

do XOR operation to add then you will get the same result as mine.

You did the simple binary operation to get the result. But if you

do XOR operation to add then you will get the same result as mine.

No matter how you do it, a multiplication is a multiplication and the

result doesn't change. You squared 31 (written in binary), the result IS

961 no matter how you got it.

Either your result is wrong, or what you want is not a square.

Nicolas

Guest

Fri Jul 19, 2013 9:16 pm

lokesh kumar wrote:

Do not consider a simple binary addition. It is an XOR operation. You did the simple binary operation to get the result. But if you do XOR operation to add then you will get the same result as mine.

So in other words, you are doing _everything_ the same as a normal

multiplication _except_ using bitwise XOR instead of adding? In

other words as you add each column you throw away any carry bits?

So for your example you have:

11111

11111

11111

11111

11111

___________

101010101

What if I have a non-trivial case like 10110? Are you doing this

as a typical multiply like:

00000

10110

10110

00000

10110

__________

100010100

Where only my final "addition" becomes an XOR?

--

Gabor

Guest

Fri Jul 19, 2013 10:23 pm

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0 " ( a 10 bit number)

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

Could anyone please help me out how to make a generalized code for squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

Guest

Sat Jul 20, 2013 12:14 am

On Saturday, July 20, 2013 2:46:16 AM UTC+5:30, Gabor Sz wrote:

lokesh kumar wrote:

Do not consider a simple binary addition. It is an XOR operation. You did the simple binary operation to get the result. But if you do XOR operation to add then you will get the same result as mine.

So in other words, you are doing _everything_ the same as a normal

multiplication _except_ using bitwise XOR instead of adding? In

other words as you add each column you throw away any carry bits?

So for your example you have:

11111

11111

11111

11111

11111

___________

101010101

What if I have a non-trivial case like 10110? Are you doing this

as a typical multiply like:

00000

10110

10110

00000

10110

__________

100010100

Where only my final "addition" becomes an XOR?

--

Gabor

Do not consider a simple binary addition. It is an XOR operation. You did the simple binary operation to get the result. But if you do XOR operation to add then you will get the same result as mine.

So in other words, you are doing _everything_ the same as a normal

multiplication _except_ using bitwise XOR instead of adding? In

other words as you add each column you throw away any carry bits?

So for your example you have:

11111

11111

11111

11111

11111

___________

101010101

What if I have a non-trivial case like 10110? Are you doing this

as a typical multiply like:

00000

10110

10110

00000

10110

__________

100010100

Where only my final "addition" becomes an XOR?

--

Gabor

Yes, the final addition becomes XOR all the times. Because I am working on Galois field. So if I take a 5-bit number and do the square of it. Then I will get a 10 bit number. But I again I will have to use the irreducible polynomial to the 10 bit number to convert it to 5 bit. That is the concept of Galois field. So basically I want to know how to make this 10 bit number by taking the square of a 5-bit number in VHDL.

Guest

Sat Jul 20, 2013 3:38 am

On 7/19/2013 6:23 PM, Fredxx wrote:

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

The syntax is not VHDL. He means for A to be a 5-bit vector

and the result ended up as:

'0' & A(4) $ '0' & A(3) $ '0' & A(2) $ '0' & A(1) $ '0' & A(0)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

For the OP clearly "multiplication" or "squaring" is incorrect. He

apparently wants a different function that is similar to multiplication

but lacks any carries on the intermediate addition.

Could anyone please help me out how to make a generalized code for

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

Guest

Sat Jul 20, 2013 8:09 am

On 7/19/2013 11:38 PM, Gabor wrote:

On 7/19/2013 6:23 PM, Fredxx wrote:

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

The syntax is not VHDL. He means for A to be a 5-bit vector

and the result ended up as:

'0' & A(4) $ '0' & A(3) $ '0' & A(2) $ '0' & A(1) $ '0' & A(0)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

For the OP clearly "multiplication" or "squaring" is incorrect. He

apparently wants a different function that is similar to multiplication

but lacks any carries on the intermediate addition.

Could anyone please help me out how to make a generalized code for

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

The syntax is not VHDL. He means for A to be a 5-bit vector

and the result ended up as:

'0' & A(4) $ '0' & A(3) $ '0' & A(2) $ '0' & A(1) $ '0' & A(0)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

For the OP clearly "multiplication" or "squaring" is incorrect. He

apparently wants a different function that is similar to multiplication

but lacks any carries on the intermediate addition.

Could anyone please help me out how to make a generalized code for

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

If he is doing a calculation on a polynomial, I understand why he wants

a multiply with no carries. Each term of the polynomial has a

coefficient which is all the terms of the same value summed together mod

2 (XOR). But I don't understand his other statements. As you showed

earlier his general form above for the product is not accurate. Or he

is saying something we don't understand.

From what I understand (or think I understand) this should be code he

could use.

subtype binary_num_5 is std_logic_vector (4 downto 0);

signal A : binary_num_5;

signal B : binary_num_5;

function square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L)

:= (others => '0');

begin

for i in arg'range loop

prod := prod XOR std_logic_vector (

SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i));

end loop;

return prod;

end square;

....

B <= square (A);

I think this will do the job but I haven't tested it, so many errors can

be present! If nothing else, it should give a good idea on how to

proceed. I will say the whole thing is a little bit simpler if it is

done with unsigned type signals rather than std_logic_vector. This

would eliminate the type casts in the loop assignment statement.

prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i));

--

Rick

Guest

Sat Jul 20, 2013 2:20 pm

On 7/20/2013 8:37 AM, lokesh kumar wrote:

On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote:

On 7/19/2013 11:38 PM, Gabor wrote:

On 7/19/2013 6:23 PM, Fredxx wrote:

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

The syntax is not VHDL. He means for A to be a 5-bit vector

and the result ended up as:

'0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

For the OP clearly "multiplication" or "squaring" is incorrect. He

apparently wants a different function that is similar to multiplication

but lacks any carries on the intermediate addition.

Could anyone please help me out how to make a generalized code for

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

If he is doing a calculation on a polynomial, I understand why he wants

a multiply with no carries. Each term of the polynomial has a

coefficient which is all the terms of the same value summed together mod

2 (XOR). But I don't understand his other statements. As you showed

earlier his general form above for the product is not accurate. Or he

is saying something we don't understand.

From what I understand (or think I understand) this should be code he

could use.

subtype binary_num_5 is std_logic_vector (4 downto 0);

signal A : binary_num_5;

signal B : binary_num_5;

function square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L)

:= (others => '0');

begin

for i in arg'range loop

prod := prod XOR std_logic_vector (

SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i));

end loop;

return prod;

end square;

...

B<= square (A);

I think this will do the job but I haven't tested it, so many errors can

be present! If nothing else, it should give a good idea on how to

proceed. I will say the whole thing is a little bit simpler if it is

done with unsigned type signals rather than std_logic_vector. This

would eliminate the type casts in the loop assignment statement.

prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i));

--

Rick

library IEEE;

On 7/19/2013 11:38 PM, Gabor wrote:

On 7/19/2013 6:23 PM, Fredxx wrote:

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

The syntax is not VHDL. He means for A to be a 5-bit vector

and the result ended up as:

'0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

For the OP clearly "multiplication" or "squaring" is incorrect. He

apparently wants a different function that is similar to multiplication

but lacks any carries on the intermediate addition.

Could anyone please help me out how to make a generalized code for

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

If he is doing a calculation on a polynomial, I understand why he wants

a multiply with no carries. Each term of the polynomial has a

coefficient which is all the terms of the same value summed together mod

2 (XOR). But I don't understand his other statements. As you showed

earlier his general form above for the product is not accurate. Or he

is saying something we don't understand.

From what I understand (or think I understand) this should be code he

could use.

subtype binary_num_5 is std_logic_vector (4 downto 0);

signal A : binary_num_5;

signal B : binary_num_5;

function square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L)

:= (others => '0');

begin

for i in arg'range loop

prod := prod XOR std_logic_vector (

SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i));

end loop;

return prod;

end square;

...

B<= square (A);

I think this will do the job but I haven't tested it, so many errors can

be present! If nothing else, it should give a good idea on how to

proceed. I will say the whole thing is a little bit simpler if it is

done with unsigned type signals rather than std_logic_vector. This

would eliminate the type casts in the loop assignment statement.

prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i));

--

Rick

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

--use work.my_package.all;

entity square_163_7_6_3 is

port (

a: in std_logic_vector(162 downto 0);

z: out std_logic_vector(162 downto 0)

);

end square_163_7_6_3;

architecture circuit of square_163_7_6_3 is

signal s, t, u, s_plus_t: std_logic_vector(162 downto 0);

signal xor1, xor2: std_logic;

begin

vector_s: for i in 0 to 80 generate

s(2*i)<= a(i);

s(2*i + 1)<= a(i+82);

end generate;

s(162)<= a(81);

vector_t1: for j in 0 to 6 generate

t(j) <= '0';

end generate;

t(7) <= a(82);

vector_t2: for i in 4 to 80 generate

t(2*i) <= a(i+7;

t(2*i + 1) <= a(i+79);

end generate;

t(162) <= a(159);

xor1 <= a(160) xor a(161);

xor2 <= a(161) xor a(162);

u(0) <= a(160);

u(1) <= a(160) xor a(162);

u(2) <= a(161);

u(3) <= xor1;

u(4) <= a(82) xor a(160);

u(5) <= xor2;

u(6) <= a(83) xor xor1;

u(7) <= '0';

u( <= a(84) xor xor1;

u(9) <= '0';

u(10) <= a(85) xor xor2;

u(11) <= '0';

u(12) <= a(86) xor a(162);

u(13) <= '0';

vector_u: for i in 7 to 80 generate

u(2*i) <= a(i+80);

u(2*i + 1) <= '0';

end generate;

u(162)<= a(161);

xor_gates1: for j in 0 to 162 generate

s_plus_t(j) <= s(j) xor t(j);

end generate;

xor_gates2: for j in 0 to 162 generate

z(j)<= s_plus_t(j) xor u(j);

end generate;

end circuit;

This the the exact code I found online, I think. But it is for 163-bit. So it is difficult to test and verify. Can you please help me to convert it for a 5-bit to make me understand it?

Many Thanks!

Hmmm... I don't think I can help you understand the code above. The

purpose of the code you posted, or at least how it was derived, is not

clear to me. If it helps you any, I have replaced it with a version

containing more white space for clarity.

Polynomial arithmetic is not my strong suit, but it seems familiar, so I

must have done it somewhere, sometime. Maybe it was that class in

multivalued logic which was actually a thinly disguised course in

abstract algebra taught in the EE department. Or more likely it is just

familiar from working with CRC calculations.

Here is my take on why you came up with the description of the formula

that you did. I am assuming that multiplication is the AND operation

and addition is the XOR operation. So '*' really means AND while '+'

really means XOR.

With that in mind here are some identities...

a(n) * a(n) = a(n)

a(n) * a(m) + a(m) * a(n) = a(n) * a(m) + a(n) * a(m) = 0

a(4 downto 0) is your input and z(8 downto 0) is your output.

a4, a3, a2, a1, a0 * a0

a4, a3, a2, a1, a0 * a1

a4, a3, a2, a1, a0 * a2

a4, a3, a2, a1, a0 * a3

a4, a3, a2, a1, a0 * a4

+ ----------------------------------

z8, z7, z6, z5, z4, z3, z2, z1, z0

z0 = a0 * a0 = a0

z1 = a0 * a1 + a1 * a0 = 0

z2 = a0 * a2 + a1 * a1 + a2 * a0 = a1

z3 = a0 * a3 + a1 * a2 + a2 * a1 + a3 * a0 = 0

z4 = a0 * a4 + a1 * a3 + a2 * a2 + a3 * a1 + a4 * a0 = a2

z5 = a1 * a4 + a2 * a3 + a3 * a2 + a4 * a1 = 0

z6 = a2 * a4 + a3 * a3 + a4 * a2 = a3

z7 = a3 * a4 + a4 * a3 = 0

z8 = a4 * a4 = a4

So this shows (at least for this case) the square of a polynomial *is*

represented by the formula you gave at the beginning (which includes one

more bit than needed).

'If we do AxA then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0"'

So here is the code for your square...

output_even: for i in 0 to 4 generate

z(2*i-1) <= a(i);

end generate;

output_odd: for i in 0 to 3 generate

z(2*i) <= '0';

end generate;

Replace the constants with the appropriate parameters and I expect you

can make a general function.

function poly_square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((2 * (arg_Len - 1)) downto 0)

:= (others => '0');

begin

for i in arg'range loop

prod(2*(i-arg_Lo)-1) := arg(i);

end loop;

return prod;

end poly_square;

....

signal A : std_logic_vector (4 downto 0);

signal B : std_logic_vector (8 downto 0);

....

B <= poly_square (A);

Again, not tested so there are likely errors.

--

Rick

Guest

Sat Jul 20, 2013 2:37 pm

On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote:

On 7/19/2013 11:38 PM, Gabor wrote:

On 7/19/2013 6:23 PM, Fredxx wrote:

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

The syntax is not VHDL. He means for A to be a 5-bit vector

and the result ended up as:

'0' & A(4) $ '0' & A(3) $ '0' & A(2) $ '0' & A(1) $ '0' & A(0)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

For the OP clearly "multiplication" or "squaring" is incorrect. He

apparently wants a different function that is similar to multiplication

but lacks any carries on the intermediate addition.

Could anyone please help me out how to make a generalized code for

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

If he is doing a calculation on a polynomial, I understand why he wants

a multiply with no carries. Each term of the polynomial has a

coefficient which is all the terms of the same value summed together mod

2 (XOR). But I don't understand his other statements. As you showed

earlier his general form above for the product is not accurate. Or he

is saying something we don't understand.

From what I understand (or think I understand) this should be code he

could use.

subtype binary_num_5 is std_logic_vector (4 downto 0);

signal A : binary_num_5;

signal B : binary_num_5;

function square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L)

:= (others => '0');

begin

for i in arg'range loop

prod := prod XOR std_logic_vector (

SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i));

end loop;

return prod;

end square;

...

B <= square (A);

I think this will do the job but I haven't tested it, so many errors can

be present! If nothing else, it should give a good idea on how to

proceed. I will say the whole thing is a little bit simpler if it is

done with unsigned type signals rather than std_logic_vector. This

would eliminate the type casts in the loop assignment statement.

prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i));

--

Rick

On 7/19/2013 6:23 PM, Fredxx wrote:

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

The syntax is not VHDL. He means for A to be a 5-bit vector

and the result ended up as:

'0' & A(4) $ '0' & A(3) $ '0' & A(2) $ '0' & A(1) $ '0' & A(0)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

For the OP clearly "multiplication" or "squaring" is incorrect. He

apparently wants a different function that is similar to multiplication

but lacks any carries on the intermediate addition.

Could anyone please help me out how to make a generalized code for

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

If he is doing a calculation on a polynomial, I understand why he wants

a multiply with no carries. Each term of the polynomial has a

coefficient which is all the terms of the same value summed together mod

2 (XOR). But I don't understand his other statements. As you showed

earlier his general form above for the product is not accurate. Or he

is saying something we don't understand.

From what I understand (or think I understand) this should be code he

could use.

subtype binary_num_5 is std_logic_vector (4 downto 0);

signal A : binary_num_5;

signal B : binary_num_5;

function square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L)

:= (others => '0');

begin

for i in arg'range loop

prod := prod XOR std_logic_vector (

SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i));

end loop;

return prod;

end square;

...

B <= square (A);

I think this will do the job but I haven't tested it, so many errors can

be present! If nothing else, it should give a good idea on how to

proceed. I will say the whole thing is a little bit simpler if it is

done with unsigned type signals rather than std_logic_vector. This

would eliminate the type casts in the loop assignment statement.

prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i));

--

Rick

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

--use work.my_package.all;

entity square_163_7_6_3 is

port (

a: in std_logic_vector(162 downto 0);

z: out std_logic_vector(162 downto 0)

);

end square_163_7_6_3;

architecture circuit of square_163_7_6_3 is

signal s, t, u, s_plus_t: std_logic_vector(162 downto 0);

signal xor1, xor2: std_logic;

begin

vector_s: for i in 0 to 80 generate s(2*i) <= a(i); s(2*i + 1) <= a(i+82); end generate;

s(162) <= a(81);

vector_t1: for j in 0 to 6 generate t(j) <= '0'; end generate;

t(7) <= a(82);

vector_t2: for i in 4 to 80 generate t(2*i) <= a(i+7; t(2*i + 1) <= a(i+79); end generate;

t(162) <= a(159);

xor1 <= a(160) xor a(161); xor2 <= a(161) xor a(162);

u(0) <= a(160); u(1) <= a(160) xor a(162); u(2) <= a(161); u(3) <= xor1;

u(4) <= a(82) xor a(160); u(5) <= xor2; u(6) <= a(83) xor xor1;

u(7) <= '0'; u( <= a(84) xor xor1; u(9) <= '0'; u(10) <= a(85) xor xor2;

u(11) <= '0'; u(12) <= a(86) xor a(162);

u(13) <= '0';

vector_u: for i in 7 to 80 generate u(2*i) <= a(i+80); u(2*i + 1) <= '0'; end generate;

u(162) <= a(161);

xor_gates1: for j in 0 to 162 generate s_plus_t(j) <= s(j) xor t(j); end generate;

xor_gates2: for j in 0 to 162 generate z(j) <= s_plus_t(j) xor u(j); end generate;

end circuit;

This the the exact code I found online, I think. But it is for 163-bit. So it is difficult to test and verify. Can you please help me to convert it for a 5-bit to make me understand it?

Many Thanks!

Guest

Sat Jul 20, 2013 3:14 pm

On 7/20/2013 10:20 AM, rickman wrote:

On 7/20/2013 8:37 AM, lokesh kumar wrote:

On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote:

On 7/19/2013 11:38 PM, Gabor wrote:

On 7/19/2013 6:23 PM, Fredxx wrote:

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

The syntax is not VHDL. He means for A to be a 5-bit vector

and the result ended up as:

'0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

For the OP clearly "multiplication" or "squaring" is incorrect. He

apparently wants a different function that is similar to multiplication

but lacks any carries on the intermediate addition.

Could anyone please help me out how to make a generalized code for

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

If he is doing a calculation on a polynomial, I understand why he wants

a multiply with no carries. Each term of the polynomial has a

coefficient which is all the terms of the same value summed together mod

2 (XOR). But I don't understand his other statements. As you showed

earlier his general form above for the product is not accurate. Or he

is saying something we don't understand.

From what I understand (or think I understand) this should be code he

could use.

subtype binary_num_5 is std_logic_vector (4 downto 0);

signal A : binary_num_5;

signal B : binary_num_5;

function square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L)

:= (others => '0');

begin

for i in arg'range loop

prod := prod XOR std_logic_vector (

SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i));

end loop;

return prod;

end square;

...

B<= square (A);

I think this will do the job but I haven't tested it, so many errors can

be present! If nothing else, it should give a good idea on how to

proceed. I will say the whole thing is a little bit simpler if it is

done with unsigned type signals rather than std_logic_vector. This

would eliminate the type casts in the loop assignment statement.

prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i));

--

Rick

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

--use work.my_package.all;

entity square_163_7_6_3 is

port (

a: in std_logic_vector(162 downto 0);

z: out std_logic_vector(162 downto 0)

);

end square_163_7_6_3;

architecture circuit of square_163_7_6_3 is

signal s, t, u, s_plus_t: std_logic_vector(162 downto 0);

signal xor1, xor2: std_logic;

begin

vector_s: for i in 0 to 80 generate

s(2*i)<= a(i);

s(2*i + 1)<= a(i+82);

end generate;

s(162)<= a(81);

vector_t1: for j in 0 to 6 generate

t(j) <= '0';

end generate;

t(7) <= a(82);

vector_t2: for i in 4 to 80 generate

t(2*i) <= a(i+7;

t(2*i + 1) <= a(i+79);

end generate;

t(162) <= a(159);

xor1 <= a(160) xor a(161);

xor2 <= a(161) xor a(162);

u(0) <= a(160);

u(1) <= a(160) xor a(162);

u(2) <= a(161);

u(3) <= xor1;

u(4) <= a(82) xor a(160);

u(5) <= xor2;

u(6) <= a(83) xor xor1;

u(7) <= '0';

u( <= a(84) xor xor1;

u(9) <= '0';

u(10) <= a(85) xor xor2;

u(11) <= '0';

u(12) <= a(86) xor a(162);

u(13) <= '0';

vector_u: for i in 7 to 80 generate

u(2*i) <= a(i+80);

u(2*i + 1) <= '0';

end generate;

u(162)<= a(161);

xor_gates1: for j in 0 to 162 generate

s_plus_t(j) <= s(j) xor t(j);

end generate;

xor_gates2: for j in 0 to 162 generate

z(j)<= s_plus_t(j) xor u(j);

end generate;

end circuit;

This the the exact code I found online, I think. But it is for

163-bit. So it is difficult to test and verify. Can you please help me

to convert it for a 5-bit to make me understand it?

Many Thanks!

Hmmm... I don't think I can help you understand the code above. The

purpose of the code you posted, or at least how it was derived, is not

clear to me. If it helps you any, I have replaced it with a version

containing more white space for clarity.

Polynomial arithmetic is not my strong suit, but it seems familiar, so I

must have done it somewhere, sometime. Maybe it was that class in

multivalued logic which was actually a thinly disguised course in

abstract algebra taught in the EE department. Or more likely it is just

familiar from working with CRC calculations.

Here is my take on why you came up with the description of the formula

that you did. I am assuming that multiplication is the AND operation and

addition is the XOR operation. So '*' really means AND while '+' really

means XOR.

With that in mind here are some identities...

a(n) * a(n) = a(n)

a(n) * a(m) + a(m) * a(n) = a(n) * a(m) + a(n) * a(m) = 0

a(4 downto 0) is your input and z(8 downto 0) is your output.

a4, a3, a2, a1, a0 * a0

a4, a3, a2, a1, a0 * a1

a4, a3, a2, a1, a0 * a2

a4, a3, a2, a1, a0 * a3

a4, a3, a2, a1, a0 * a4

+ ----------------------------------

z8, z7, z6, z5, z4, z3, z2, z1, z0

z0 = a0 * a0 = a0

z1 = a0 * a1 + a1 * a0 = 0

z2 = a0 * a2 + a1 * a1 + a2 * a0 = a1

z3 = a0 * a3 + a1 * a2 + a2 * a1 + a3 * a0 = 0

z4 = a0 * a4 + a1 * a3 + a2 * a2 + a3 * a1 + a4 * a0 = a2

z5 = a1 * a4 + a2 * a3 + a3 * a2 + a4 * a1 = 0

z6 = a2 * a4 + a3 * a3 + a4 * a2 = a3

z7 = a3 * a4 + a4 * a3 = 0

z8 = a4 * a4 = a4

So this shows (at least for this case) the square of a polynomial *is*

represented by the formula you gave at the beginning (which includes one

more bit than needed).

'If we do AxA then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0"'

So here is the code for your square...

output_even: for i in 0 to 4 generate

z(2*i-1) <= a(i);

end generate;

output_odd: for i in 0 to 3 generate

z(2*i) <= '0';

end generate;

On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote:

On 7/19/2013 11:38 PM, Gabor wrote:

On 7/19/2013 6:23 PM, Fredxx wrote:

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

The syntax is not VHDL. He means for A to be a 5-bit vector

and the result ended up as:

'0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

For the OP clearly "multiplication" or "squaring" is incorrect. He

apparently wants a different function that is similar to multiplication

but lacks any carries on the intermediate addition.

Could anyone please help me out how to make a generalized code for

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

If he is doing a calculation on a polynomial, I understand why he wants

a multiply with no carries. Each term of the polynomial has a

coefficient which is all the terms of the same value summed together mod

2 (XOR). But I don't understand his other statements. As you showed

earlier his general form above for the product is not accurate. Or he

is saying something we don't understand.

From what I understand (or think I understand) this should be code he

could use.

subtype binary_num_5 is std_logic_vector (4 downto 0);

signal A : binary_num_5;

signal B : binary_num_5;

function square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L)

:= (others => '0');

begin

for i in arg'range loop

prod := prod XOR std_logic_vector (

SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i));

end loop;

return prod;

end square;

...

B<= square (A);

I think this will do the job but I haven't tested it, so many errors can

be present! If nothing else, it should give a good idea on how to

proceed. I will say the whole thing is a little bit simpler if it is

done with unsigned type signals rather than std_logic_vector. This

would eliminate the type casts in the loop assignment statement.

prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i));

--

Rick

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

--use work.my_package.all;

entity square_163_7_6_3 is

port (

a: in std_logic_vector(162 downto 0);

z: out std_logic_vector(162 downto 0)

);

end square_163_7_6_3;

architecture circuit of square_163_7_6_3 is

signal s, t, u, s_plus_t: std_logic_vector(162 downto 0);

signal xor1, xor2: std_logic;

begin

vector_s: for i in 0 to 80 generate

s(2*i)<= a(i);

s(2*i + 1)<= a(i+82);

end generate;

s(162)<= a(81);

vector_t1: for j in 0 to 6 generate

t(j) <= '0';

end generate;

t(7) <= a(82);

vector_t2: for i in 4 to 80 generate

t(2*i) <= a(i+7;

t(2*i + 1) <= a(i+79);

end generate;

t(162) <= a(159);

xor1 <= a(160) xor a(161);

xor2 <= a(161) xor a(162);

u(0) <= a(160);

u(1) <= a(160) xor a(162);

u(2) <= a(161);

u(3) <= xor1;

u(4) <= a(82) xor a(160);

u(5) <= xor2;

u(6) <= a(83) xor xor1;

u(7) <= '0';

u( <= a(84) xor xor1;

u(9) <= '0';

u(10) <= a(85) xor xor2;

u(11) <= '0';

u(12) <= a(86) xor a(162);

u(13) <= '0';

vector_u: for i in 7 to 80 generate

u(2*i) <= a(i+80);

u(2*i + 1) <= '0';

end generate;

u(162)<= a(161);

xor_gates1: for j in 0 to 162 generate

s_plus_t(j) <= s(j) xor t(j);

end generate;

xor_gates2: for j in 0 to 162 generate

z(j)<= s_plus_t(j) xor u(j);

end generate;

end circuit;

This the the exact code I found online, I think. But it is for

163-bit. So it is difficult to test and verify. Can you please help me

to convert it for a 5-bit to make me understand it?

Many Thanks!

Hmmm... I don't think I can help you understand the code above. The

purpose of the code you posted, or at least how it was derived, is not

clear to me. If it helps you any, I have replaced it with a version

containing more white space for clarity.

Polynomial arithmetic is not my strong suit, but it seems familiar, so I

must have done it somewhere, sometime. Maybe it was that class in

multivalued logic which was actually a thinly disguised course in

abstract algebra taught in the EE department. Or more likely it is just

familiar from working with CRC calculations.

Here is my take on why you came up with the description of the formula

that you did. I am assuming that multiplication is the AND operation and

addition is the XOR operation. So '*' really means AND while '+' really

means XOR.

With that in mind here are some identities...

a(n) * a(n) = a(n)

a(n) * a(m) + a(m) * a(n) = a(n) * a(m) + a(n) * a(m) = 0

a(4 downto 0) is your input and z(8 downto 0) is your output.

a4, a3, a2, a1, a0 * a0

a4, a3, a2, a1, a0 * a1

a4, a3, a2, a1, a0 * a2

a4, a3, a2, a1, a0 * a3

a4, a3, a2, a1, a0 * a4

+ ----------------------------------

z8, z7, z6, z5, z4, z3, z2, z1, z0

z0 = a0 * a0 = a0

z1 = a0 * a1 + a1 * a0 = 0

z2 = a0 * a2 + a1 * a1 + a2 * a0 = a1

z3 = a0 * a3 + a1 * a2 + a2 * a1 + a3 * a0 = 0

z4 = a0 * a4 + a1 * a3 + a2 * a2 + a3 * a1 + a4 * a0 = a2

z5 = a1 * a4 + a2 * a3 + a3 * a2 + a4 * a1 = 0

z6 = a2 * a4 + a3 * a3 + a4 * a2 = a3

z7 = a3 * a4 + a4 * a3 = 0

z8 = a4 * a4 = a4

So this shows (at least for this case) the square of a polynomial *is*

represented by the formula you gave at the beginning (which includes one

more bit than needed).

'If we do AxA then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0"'

So here is the code for your square...

output_even: for i in 0 to 4 generate

z(2*i-1) <= a(i);

end generate;

output_odd: for i in 0 to 3 generate

z(2*i) <= '0';

end generate;

Sure enough, there is an error (at least one). I found it by reading my

labels...

output_even: for i in 0 to 4 generate

z(2*i) <= a(i);

end generate;

output_odd: for i in 0 to 3 generate

z(2*i+1) <= '0';

end generate;

--- Same error in this code ---

function poly_square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((2 * (arg_Len - 1)) downto 0)

:= (others => '0');

begin

for i in arg'range loop

prod(2*(i-arg_Lo)) := arg(i);

end loop;

return prod;

end poly_square;

--

Rick

Guest

Sat Jul 20, 2013 5:46 pm

On Saturday, July 20, 2013 7:50:20 PM UTC+5:30, rickman wrote:

On 7/20/2013 8:37 AM, lokesh kumar wrote:

On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote:

On 7/19/2013 11:38 PM, Gabor wrote:

On 7/19/2013 6:23 PM, Fredxx wrote:

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

The syntax is not VHDL. He means for A to be a 5-bit vector

and the result ended up as:

'0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

For the OP clearly "multiplication" or "squaring" is incorrect. He

apparently wants a different function that is similar to multiplication

but lacks any carries on the intermediate addition.

Could anyone please help me out how to make a generalized code for

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

If he is doing a calculation on a polynomial, I understand why he wants

a multiply with no carries. Each term of the polynomial has a

coefficient which is all the terms of the same value summed together mod

2 (XOR). But I don't understand his other statements. As you showed

earlier his general form above for the product is not accurate. Or he

is saying something we don't understand.

From what I understand (or think I understand) this should be code he

could use.

subtype binary_num_5 is std_logic_vector (4 downto 0);

signal A : binary_num_5;

signal B : binary_num_5;

function square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L)

:= (others => '0');

begin

for i in arg'range loop

prod := prod XOR std_logic_vector (

SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i));

end loop;

return prod;

end square;

...

B<= square (A);

I think this will do the job but I haven't tested it, so many errors can

be present! If nothing else, it should give a good idea on how to

proceed. I will say the whole thing is a little bit simpler if it is

done with unsigned type signals rather than std_logic_vector. This

would eliminate the type casts in the loop assignment statement.

prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i));

--

Rick

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

--use work.my_package.all;

entity square_163_7_6_3 is

port (

a: in std_logic_vector(162 downto 0);

z: out std_logic_vector(162 downto 0)

);

end square_163_7_6_3;

architecture circuit of square_163_7_6_3 is

signal s, t, u, s_plus_t: std_logic_vector(162 downto 0);

signal xor1, xor2: std_logic;

begin

vector_s: for i in 0 to 80 generate

s(2*i)<= a(i);

s(2*i + 1)<= a(i+82);

end generate;

s(162)<= a(81);

vector_t1: for j in 0 to 6 generate

t(j) <= '0';

end generate;

t(7) <= a(82);

vector_t2: for i in 4 to 80 generate

t(2*i) <= a(i+7;

t(2*i + 1) <= a(i+79);

end generate;

t(162) <= a(159);

xor1 <= a(160) xor a(161);

xor2 <= a(161) xor a(162);

u(0) <= a(160);

u(1) <= a(160) xor a(162);

u(2) <= a(161);

u(3) <= xor1;

u(4) <= a(82) xor a(160);

u(5) <= xor2;

u(6) <= a(83) xor xor1;

u(7) <= '0';

u( <= a(84) xor xor1;

u(9) <= '0';

u(10) <= a(85) xor xor2;

u(11) <= '0';

u(12) <= a(86) xor a(162);

u(13) <= '0';

vector_u: for i in 7 to 80 generate

u(2*i) <= a(i+80);

u(2*i + 1) <= '0';

end generate;

u(162)<= a(161);

xor_gates1: for j in 0 to 162 generate

s_plus_t(j) <= s(j) xor t(j);

end generate;

xor_gates2: for j in 0 to 162 generate

z(j)<= s_plus_t(j) xor u(j);

end generate;

end circuit;

This the the exact code I found online, I think. But it is for 163-bit. So it is difficult to test and verify. Can you please help me to convert it for a 5-bit to make me understand it?

Many Thanks!

Hmmm... I don't think I can help you understand the code above. The

purpose of the code you posted, or at least how it was derived, is not

clear to me. If it helps you any, I have replaced it with a version

containing more white space for clarity.

Polynomial arithmetic is not my strong suit, but it seems familiar, so I

must have done it somewhere, sometime. Maybe it was that class in

multivalued logic which was actually a thinly disguised course in

abstract algebra taught in the EE department. Or more likely it is just

familiar from working with CRC calculations.

Here is my take on why you came up with the description of the formula

that you did. I am assuming that multiplication is the AND operation

and addition is the XOR operation. So '*' really means AND while '+'

really means XOR.

With that in mind here are some identities...

a(n) * a(n) = a(n)

a(n) * a(m) + a(m) * a(n) = a(n) * a(m) + a(n) * a(m) = 0

a(4 downto 0) is your input and z(8 downto 0) is your output.

a4, a3, a2, a1, a0 * a0

a4, a3, a2, a1, a0 * a1

a4, a3, a2, a1, a0 * a2

a4, a3, a2, a1, a0 * a3

a4, a3, a2, a1, a0 * a4

+ ----------------------------------

z8, z7, z6, z5, z4, z3, z2, z1, z0

z0 = a0 * a0 = a0

z1 = a0 * a1 + a1 * a0 = 0

z2 = a0 * a2 + a1 * a1 + a2 * a0 = a1

z3 = a0 * a3 + a1 * a2 + a2 * a1 + a3 * a0 = 0

z4 = a0 * a4 + a1 * a3 + a2 * a2 + a3 * a1 + a4 * a0 = a2

z5 = a1 * a4 + a2 * a3 + a3 * a2 + a4 * a1 = 0

z6 = a2 * a4 + a3 * a3 + a4 * a2 = a3

z7 = a3 * a4 + a4 * a3 = 0

z8 = a4 * a4 = a4

So this shows (at least for this case) the square of a polynomial *is*

represented by the formula you gave at the beginning (which includes one

more bit than needed).

'If we do AxA then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0"'

So here is the code for your square...

output_even: for i in 0 to 4 generate

z(2*i-1) <= a(i);

end generate;

output_odd: for i in 0 to 3 generate

z(2*i) <= '0';

end generate;

Replace the constants with the appropriate parameters and I expect you

can make a general function.

function poly_square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((2 * (arg_Len - 1)) downto 0)

:= (others => '0');

begin

for i in arg'range loop

prod(2*(i-arg_Lo)-1) := arg(i);

end loop;

return prod;

end poly_square;

...

signal A : std_logic_vector (4 downto 0);

signal B : std_logic_vector (8 downto 0);

...

B <= poly_square (A);

Again, not tested so there are likely errors.

--

Rick

It is a bit confusing to me.

On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote:

On 7/19/2013 11:38 PM, Gabor wrote:

On 7/19/2013 6:23 PM, Fredxx wrote:

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

The syntax is not VHDL. He means for A to be a 5-bit vector

and the result ended up as:

'0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

For the OP clearly "multiplication" or "squaring" is incorrect. He

apparently wants a different function that is similar to multiplication

but lacks any carries on the intermediate addition.

Could anyone please help me out how to make a generalized code for

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

If he is doing a calculation on a polynomial, I understand why he wants

a multiply with no carries. Each term of the polynomial has a

coefficient which is all the terms of the same value summed together mod

2 (XOR). But I don't understand his other statements. As you showed

earlier his general form above for the product is not accurate. Or he

is saying something we don't understand.

From what I understand (or think I understand) this should be code he

could use.

subtype binary_num_5 is std_logic_vector (4 downto 0);

signal A : binary_num_5;

signal B : binary_num_5;

function square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L)

:= (others => '0');

begin

for i in arg'range loop

prod := prod XOR std_logic_vector (

SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i));

end loop;

return prod;

end square;

...

B<= square (A);

I think this will do the job but I haven't tested it, so many errors can

be present! If nothing else, it should give a good idea on how to

proceed. I will say the whole thing is a little bit simpler if it is

done with unsigned type signals rather than std_logic_vector. This

would eliminate the type casts in the loop assignment statement.

prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i));

--

Rick

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

--use work.my_package.all;

entity square_163_7_6_3 is

port (

a: in std_logic_vector(162 downto 0);

z: out std_logic_vector(162 downto 0)

);

end square_163_7_6_3;

architecture circuit of square_163_7_6_3 is

signal s, t, u, s_plus_t: std_logic_vector(162 downto 0);

signal xor1, xor2: std_logic;

begin

vector_s: for i in 0 to 80 generate

s(2*i)<= a(i);

s(2*i + 1)<= a(i+82);

end generate;

s(162)<= a(81);

vector_t1: for j in 0 to 6 generate

t(j) <= '0';

end generate;

t(7) <= a(82);

vector_t2: for i in 4 to 80 generate

t(2*i) <= a(i+7;

t(2*i + 1) <= a(i+79);

end generate;

t(162) <= a(159);

xor1 <= a(160) xor a(161);

xor2 <= a(161) xor a(162);

u(0) <= a(160);

u(1) <= a(160) xor a(162);

u(2) <= a(161);

u(3) <= xor1;

u(4) <= a(82) xor a(160);

u(5) <= xor2;

u(6) <= a(83) xor xor1;

u(7) <= '0';

u( <= a(84) xor xor1;

u(9) <= '0';

u(10) <= a(85) xor xor2;

u(11) <= '0';

u(12) <= a(86) xor a(162);

u(13) <= '0';

vector_u: for i in 7 to 80 generate

u(2*i) <= a(i+80);

u(2*i + 1) <= '0';

end generate;

u(162)<= a(161);

xor_gates1: for j in 0 to 162 generate

s_plus_t(j) <= s(j) xor t(j);

end generate;

xor_gates2: for j in 0 to 162 generate

z(j)<= s_plus_t(j) xor u(j);

end generate;

end circuit;

This the the exact code I found online, I think. But it is for 163-bit. So it is difficult to test and verify. Can you please help me to convert it for a 5-bit to make me understand it?

Many Thanks!

Hmmm... I don't think I can help you understand the code above. The

purpose of the code you posted, or at least how it was derived, is not

clear to me. If it helps you any, I have replaced it with a version

containing more white space for clarity.

Polynomial arithmetic is not my strong suit, but it seems familiar, so I

must have done it somewhere, sometime. Maybe it was that class in

multivalued logic which was actually a thinly disguised course in

abstract algebra taught in the EE department. Or more likely it is just

familiar from working with CRC calculations.

Here is my take on why you came up with the description of the formula

that you did. I am assuming that multiplication is the AND operation

and addition is the XOR operation. So '*' really means AND while '+'

really means XOR.

With that in mind here are some identities...

a(n) * a(n) = a(n)

a(n) * a(m) + a(m) * a(n) = a(n) * a(m) + a(n) * a(m) = 0

a(4 downto 0) is your input and z(8 downto 0) is your output.

a4, a3, a2, a1, a0 * a0

a4, a3, a2, a1, a0 * a1

a4, a3, a2, a1, a0 * a2

a4, a3, a2, a1, a0 * a3

a4, a3, a2, a1, a0 * a4

+ ----------------------------------

z8, z7, z6, z5, z4, z3, z2, z1, z0

z0 = a0 * a0 = a0

z1 = a0 * a1 + a1 * a0 = 0

z2 = a0 * a2 + a1 * a1 + a2 * a0 = a1

z3 = a0 * a3 + a1 * a2 + a2 * a1 + a3 * a0 = 0

z4 = a0 * a4 + a1 * a3 + a2 * a2 + a3 * a1 + a4 * a0 = a2

z5 = a1 * a4 + a2 * a3 + a3 * a2 + a4 * a1 = 0

z6 = a2 * a4 + a3 * a3 + a4 * a2 = a3

z7 = a3 * a4 + a4 * a3 = 0

z8 = a4 * a4 = a4

So this shows (at least for this case) the square of a polynomial *is*

represented by the formula you gave at the beginning (which includes one

more bit than needed).

'If we do AxA then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0"'

So here is the code for your square...

output_even: for i in 0 to 4 generate

z(2*i-1) <= a(i);

end generate;

output_odd: for i in 0 to 3 generate

z(2*i) <= '0';

end generate;

Replace the constants with the appropriate parameters and I expect you

can make a general function.

function poly_square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((2 * (arg_Len - 1)) downto 0)

:= (others => '0');

begin

for i in arg'range loop

prod(2*(i-arg_Lo)-1) := arg(i);

end loop;

return prod;

end poly_square;

...

signal A : std_logic_vector (4 downto 0);

signal B : std_logic_vector (8 downto 0);

...

B <= poly_square (A);

Again, not tested so there are likely errors.

--

Rick

It is a bit confusing to me.

Can I have your email id please? I can send you a relevant paper for the circuit with the algorithm. May be you will be able to understand it. I am unable to find more information related to it.

vector_s: for i in 0 to 80 generate s(2*i) <= a(i); s(2*i + 1) <= a(i+82); end generate;

s(162) <= a(81);

vector_t1: for j in 0 to 6 generate t(j) <= '0'; end generate;

t(7) <= a(82);

vector_t2: for i in 4 to 80 generate t(2*i) <= a(i+7; t(2*i + 1) <= a(i+79); end generate;

t(162) <= a(159);

For a 163-bit circuit, especially I do not understand this part. So please help me out.

Thanks!

Guest

Sat Jul 20, 2013 7:23 pm

On 7/20/2013 11:46 AM, lokesh kumar wrote:

On Saturday, July 20, 2013 7:50:20 PM UTC+5:30, rickman wrote:

On 7/20/2013 8:37 AM, lokesh kumar wrote:

On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote:

On 7/19/2013 11:38 PM, Gabor wrote:

On 7/19/2013 6:23 PM, Fredxx wrote:

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

The syntax is not VHDL. He means for A to be a 5-bit vector

and the result ended up as:

'0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

For the OP clearly "multiplication" or "squaring" is incorrect. He

apparently wants a different function that is similar to multiplication

but lacks any carries on the intermediate addition.

Could anyone please help me out how to make a generalized code for

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

If he is doing a calculation on a polynomial, I understand why he wants

a multiply with no carries. Each term of the polynomial has a

coefficient which is all the terms of the same value summed together mod

2 (XOR). But I don't understand his other statements. As you showed

earlier his general form above for the product is not accurate. Or he

is saying something we don't understand.

From what I understand (or think I understand) this should be code he

could use.

subtype binary_num_5 is std_logic_vector (4 downto 0);

signal A : binary_num_5;

signal B : binary_num_5;

function square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L)

:= (others => '0');

begin

for i in arg'range loop

prod := prod XOR std_logic_vector (

SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i));

end loop;

return prod;

end square;

...

B<= square (A);

I think this will do the job but I haven't tested it, so many errors can

be present! If nothing else, it should give a good idea on how to

proceed. I will say the whole thing is a little bit simpler if it is

done with unsigned type signals rather than std_logic_vector. This

would eliminate the type casts in the loop assignment statement.

prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i));

--

Rick

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

--use work.my_package.all;

entity square_163_7_6_3 is

port (

a: in std_logic_vector(162 downto 0);

z: out std_logic_vector(162 downto 0)

);

end square_163_7_6_3;

architecture circuit of square_163_7_6_3 is

signal s, t, u, s_plus_t: std_logic_vector(162 downto 0);

signal xor1, xor2: std_logic;

begin

vector_s: for i in 0 to 80 generate

s(2*i)<= a(i);

s(2*i + 1)<= a(i+82);

end generate;

s(162)<= a(81);

vector_t1: for j in 0 to 6 generate

t(j)<= '0';

end generate;

t(7)<= a(82);

vector_t2: for i in 4 to 80 generate

t(2*i)<= a(i+7;

t(2*i + 1)<= a(i+79);

end generate;

t(162)<= a(159);

xor1<= a(160) xor a(161);

xor2<= a(161) xor a(162);

u(0)<= a(160);

u(1)<= a(160) xor a(162);

u(2)<= a(161);

u(3)<= xor1;

u(4)<= a(82) xor a(160);

u(5)<= xor2;

u(6)<= a(83) xor xor1;

u(7)<= '0';

u(<= a(84) xor xor1;

u(9)<= '0';

u(10)<= a(85) xor xor2;

u(11)<= '0';

u(12)<= a(86) xor a(162);

u(13)<= '0';

vector_u: for i in 7 to 80 generate

u(2*i)<= a(i+80);

u(2*i + 1)<= '0';

end generate;

u(162)<= a(161);

xor_gates1: for j in 0 to 162 generate

s_plus_t(j)<= s(j) xor t(j);

end generate;

xor_gates2: for j in 0 to 162 generate

z(j)<= s_plus_t(j) xor u(j);

end generate;

end circuit;

This the the exact code I found online, I think. But it is for 163-bit. So it is difficult to test and verify. Can you please help me to convert it for a 5-bit to make me understand it?

Many Thanks!

Hmmm... I don't think I can help you understand the code above. The

purpose of the code you posted, or at least how it was derived, is not

clear to me. If it helps you any, I have replaced it with a version

containing more white space for clarity.

Polynomial arithmetic is not my strong suit, but it seems familiar, so I

must have done it somewhere, sometime. Maybe it was that class in

multivalued logic which was actually a thinly disguised course in

abstract algebra taught in the EE department. Or more likely it is just

familiar from working with CRC calculations.

Here is my take on why you came up with the description of the formula

that you did. I am assuming that multiplication is the AND operation

and addition is the XOR operation. So '*' really means AND while '+'

really means XOR.

With that in mind here are some identities...

a(n) * a(n) = a(n)

a(n) * a(m) + a(m) * a(n) = a(n) * a(m) + a(n) * a(m) = 0

a(4 downto 0) is your input and z(8 downto 0) is your output.

a4, a3, a2, a1, a0 * a0

a4, a3, a2, a1, a0 * a1

a4, a3, a2, a1, a0 * a2

a4, a3, a2, a1, a0 * a3

a4, a3, a2, a1, a0 * a4

+ ----------------------------------

z8, z7, z6, z5, z4, z3, z2, z1, z0

z0 = a0 * a0 = a0

z1 = a0 * a1 + a1 * a0 = 0

z2 = a0 * a2 + a1 * a1 + a2 * a0 = a1

z3 = a0 * a3 + a1 * a2 + a2 * a1 + a3 * a0 = 0

z4 = a0 * a4 + a1 * a3 + a2 * a2 + a3 * a1 + a4 * a0 = a2

z5 = a1 * a4 + a2 * a3 + a3 * a2 + a4 * a1 = 0

z6 = a2 * a4 + a3 * a3 + a4 * a2 = a3

z7 = a3 * a4 + a4 * a3 = 0

z8 = a4 * a4 = a4

So this shows (at least for this case) the square of a polynomial *is*

represented by the formula you gave at the beginning (which includes one

more bit than needed).

'If we do AxA then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0"'

So here is the code for your square...

output_even: for i in 0 to 4 generate

z(2*i-1)<= a(i);

end generate;

output_odd: for i in 0 to 3 generate

z(2*i)<= '0';

end generate;

Replace the constants with the appropriate parameters and I expect you

can make a general function.

function poly_square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((2 * (arg_Len - 1)) downto 0)

:= (others => '0');

begin

for i in arg'range loop

prod(2*(i-arg_Lo)-1) := arg(i);

end loop;

return prod;

end poly_square;

...

signal A : std_logic_vector (4 downto 0);

signal B : std_logic_vector (8 downto 0);

...

B<= poly_square (A);

Again, not tested so there are likely errors.

--

Rick

It is a bit confusing to me.

Can I have your email id please? I can send you a relevant paper for the circuit with the algorithm. May be you will be able to understand it. I am unable to find more information related to it.

vector_s: for i in 0 to 80 generate s(2*i)<= a(i); s(2*i + 1)<= a(i+82); end generate;

s(162)<= a(81);

On 7/20/2013 8:37 AM, lokesh kumar wrote:

On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote:

On 7/19/2013 11:38 PM, Gabor wrote:

On 7/19/2013 6:23 PM, Fredxx wrote:

On 19/07/2013 18:27, lokesh kumar wrote:

Hi,

Can anyone help me to design a code to square binary number?

Suppose "A" is a 5 bit number (a4a3a2a1a0)

If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0

a0 " ( a 10 bit number)

All these numbers look bigger than 5 or 10 bits!

The syntax is not VHDL. He means for A to be a 5-bit vector

and the result ended up as:

'0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0)

For example : Suppose A= 11111

Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for

the adding to get the final result).

31 x 31 = 961 (11 1100 0001)

So clearly XORing is incorrect.

For the OP clearly "multiplication" or "squaring" is incorrect. He

apparently wants a different function that is similar to multiplication

but lacks any carries on the intermediate addition.

Could anyone please help me out how to make a generalized code for

squaring of a 5-bit number to get an output like this?

A square operation is precisely that, A * A. Most FPGAs have some

pretty good multipliers, best to use them.

If he is doing a calculation on a polynomial, I understand why he wants

a multiply with no carries. Each term of the polynomial has a

coefficient which is all the terms of the same value summed together mod

2 (XOR). But I don't understand his other statements. As you showed

earlier his general form above for the product is not accurate. Or he

is saying something we don't understand.

From what I understand (or think I understand) this should be code he

could use.

subtype binary_num_5 is std_logic_vector (4 downto 0);

signal A : binary_num_5;

signal B : binary_num_5;

function square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L)

:= (others => '0');

begin

for i in arg'range loop

prod := prod XOR std_logic_vector (

SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i));

end loop;

return prod;

end square;

...

B<= square (A);

I think this will do the job but I haven't tested it, so many errors can

be present! If nothing else, it should give a good idea on how to

proceed. I will say the whole thing is a little bit simpler if it is

done with unsigned type signals rather than std_logic_vector. This

would eliminate the type casts in the loop assignment statement.

prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i));

--

Rick

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

--use work.my_package.all;

entity square_163_7_6_3 is

port (

a: in std_logic_vector(162 downto 0);

z: out std_logic_vector(162 downto 0)

);

end square_163_7_6_3;

architecture circuit of square_163_7_6_3 is

signal s, t, u, s_plus_t: std_logic_vector(162 downto 0);

signal xor1, xor2: std_logic;

begin

vector_s: for i in 0 to 80 generate

s(2*i)<= a(i);

s(2*i + 1)<= a(i+82);

end generate;

s(162)<= a(81);

vector_t1: for j in 0 to 6 generate

t(j)<= '0';

end generate;

t(7)<= a(82);

vector_t2: for i in 4 to 80 generate

t(2*i)<= a(i+7;

t(2*i + 1)<= a(i+79);

end generate;

t(162)<= a(159);

xor1<= a(160) xor a(161);

xor2<= a(161) xor a(162);

u(0)<= a(160);

u(1)<= a(160) xor a(162);

u(2)<= a(161);

u(3)<= xor1;

u(4)<= a(82) xor a(160);

u(5)<= xor2;

u(6)<= a(83) xor xor1;

u(7)<= '0';

u(<= a(84) xor xor1;

u(9)<= '0';

u(10)<= a(85) xor xor2;

u(11)<= '0';

u(12)<= a(86) xor a(162);

u(13)<= '0';

vector_u: for i in 7 to 80 generate

u(2*i)<= a(i+80);

u(2*i + 1)<= '0';

end generate;

u(162)<= a(161);

xor_gates1: for j in 0 to 162 generate

s_plus_t(j)<= s(j) xor t(j);

end generate;

xor_gates2: for j in 0 to 162 generate

z(j)<= s_plus_t(j) xor u(j);

end generate;

end circuit;

This the the exact code I found online, I think. But it is for 163-bit. So it is difficult to test and verify. Can you please help me to convert it for a 5-bit to make me understand it?

Many Thanks!

Hmmm... I don't think I can help you understand the code above. The

purpose of the code you posted, or at least how it was derived, is not

clear to me. If it helps you any, I have replaced it with a version

containing more white space for clarity.

Polynomial arithmetic is not my strong suit, but it seems familiar, so I

must have done it somewhere, sometime. Maybe it was that class in

multivalued logic which was actually a thinly disguised course in

abstract algebra taught in the EE department. Or more likely it is just

familiar from working with CRC calculations.

Here is my take on why you came up with the description of the formula

that you did. I am assuming that multiplication is the AND operation

and addition is the XOR operation. So '*' really means AND while '+'

really means XOR.

With that in mind here are some identities...

a(n) * a(n) = a(n)

a(n) * a(m) + a(m) * a(n) = a(n) * a(m) + a(n) * a(m) = 0

a(4 downto 0) is your input and z(8 downto 0) is your output.

a4, a3, a2, a1, a0 * a0

a4, a3, a2, a1, a0 * a1

a4, a3, a2, a1, a0 * a2

a4, a3, a2, a1, a0 * a3

a4, a3, a2, a1, a0 * a4

+ ----------------------------------

z8, z7, z6, z5, z4, z3, z2, z1, z0

z0 = a0 * a0 = a0

z1 = a0 * a1 + a1 * a0 = 0

z2 = a0 * a2 + a1 * a1 + a2 * a0 = a1

z3 = a0 * a3 + a1 * a2 + a2 * a1 + a3 * a0 = 0

z4 = a0 * a4 + a1 * a3 + a2 * a2 + a3 * a1 + a4 * a0 = a2

z5 = a1 * a4 + a2 * a3 + a3 * a2 + a4 * a1 = 0

z6 = a2 * a4 + a3 * a3 + a4 * a2 = a3

z7 = a3 * a4 + a4 * a3 = 0

z8 = a4 * a4 = a4

So this shows (at least for this case) the square of a polynomial *is*

represented by the formula you gave at the beginning (which includes one

more bit than needed).

'If we do AxA then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0"'

So here is the code for your square...

output_even: for i in 0 to 4 generate

z(2*i-1)<= a(i);

end generate;

output_odd: for i in 0 to 3 generate

z(2*i)<= '0';

end generate;

Replace the constants with the appropriate parameters and I expect you

can make a general function.

function poly_square (arg : std_logic_vector) return std_logic_vector is

constant arg_Hi : integer := arg'HIGH;

constant arg_Lo : integer := arg'LOW;

constant arg_Len : integer := arg'LENGTH;

variable prod : std_logic_vector ((2 * (arg_Len - 1)) downto 0)

:= (others => '0');

begin

for i in arg'range loop

prod(2*(i-arg_Lo)-1) := arg(i);

end loop;

return prod;

end poly_square;

...

signal A : std_logic_vector (4 downto 0);

signal B : std_logic_vector (8 downto 0);

...

B<= poly_square (A);

Again, not tested so there are likely errors.

--

Rick

It is a bit confusing to me.

Can I have your email id please? I can send you a relevant paper for the circuit with the algorithm. May be you will be able to understand it. I am unable to find more information related to it.

vector_s: for i in 0 to 80 generate s(2*i)<= a(i); s(2*i + 1)<= a(i+82); end generate;

s(162)<= a(81);

Do you understand what this code is doing? It is generating the signal

s() from the signal a(). Is that clear?

vector_t1: for j in 0 to 6 generate t(j)<= '0'; end generate;

t(7)<= a(82);

vector_t2: for i in 4 to 80 generate t(2*i)<= a(i+7; t(2*i + 1)<= a(i+79); end generate;

t(162)<= a(159);

t(7)<= a(82);

vector_t2: for i in 4 to 80 generate t(2*i)<= a(i+7; t(2*i + 1)<= a(i+79); end generate;

t(162)<= a(159);

This code generates t() from a().

For a 163-bit circuit, especially I do not understand this part. So please help me out.

Thanks!

Thanks!

I don't get it either. What are a(), s(), t() and z()? Is this

supposed to be squaring a() to get z()? If so, why is a() the same

length as z()? I can't find any of this code using Google.

I got your other email which was largely the same as your earlier post I

think. I prefer to discuss this here. There may be others who would

like to understand this or who can explain it. In fact, you might try

explaining what you are doing and ask how to do this in other groups

such as comp.dsp. Working from an undocumented code section is not a

great way to understand an algorithm.

I can't tell you anything about the code you posted. I have no idea why

they are doing all the calculations they are doing. I can read the

VHDL, but I can't read the mind of the person who wrote it.

I might be able to help you figure this out if you give more background.

What are you trying to do? What is the bigger picture? There is

often more than one way to skin a cat. If I understand what you are

trying to do with polynomials I think I have already explained what you

need to do to square a() and given you code to do it. If I don't

understand, perhaps you can explain better?

BTW, when you use Google Groups to post in newsgroups you need to fix

your quoted lines. Google Groups adds blank lines between the lines of

the quoted material and after a couple of quotes becomes unreadable.

--

Rick

Guest

Sat Jul 20, 2013 7:50 pm

On 20/07/2013 20:23, rickman wrote:

On 7/20/2013 11:46 AM, lokesh kumar wrote:

On Saturday, July 20, 2013 7:50:20 PM UTC+5:30, rickman wrote:

On 7/20/2013 8:37 AM, lokesh kumar wrote:

snip

On Saturday, July 20, 2013 7:50:20 PM UTC+5:30, rickman wrote:

On 7/20/2013 8:37 AM, lokesh kumar wrote:

snip

Rick

It is a bit confusing to me. Can I have your email id please? I can

send you a relevant paper for the circuit with the algorithm. May

be you will be able to understand it. I am unable to find more

information related to it.

vector_s: for i in 0 to 80 generate s(2*i)<= a(i); s(2*i + 1)<=

a(i+82); end generate; s(162)<= a(81);

Do you understand what this code is doing? It is generating the

signal s() from the signal a(). Is that clear?

vector_t1: for j in 0 to 6 generate t(j)<= '0'; end generate;

t(7)<= a(82); vector_t2: for i in 4 to 80 generate t(2*i)<=

a(i+7; t(2*i + 1)<= a(i+79); end generate; t(162)<= a(159);

This code generates t() from a().

For a 163-bit circuit, especially I do not understand this part. So

please help me out. Thanks!

I don't get it either. What are a(), s(), t() and z()? Is this

supposed to be squaring a() to get z()? If so, why is a() the same

length as z()? I can't find any of this code using Google.

I got your other email which was largely the same as your earlier

post I think. I prefer to discuss this here. There may be others

who would like to understand this or who can explain it. In fact,

you might try explaining what you are doing and ask how to do this in

other groups such as comp.dsp. Working from an undocumented code

section is not a great way to understand an algorithm.

I can't tell you anything about the code you posted. I have no idea

why they are doing all the calculations they are doing. I can read

the VHDL, but I can't read the mind of the person who wrote it.

I might be able to help you figure this out if you give more

background. What are you trying to do? What is the bigger picture?

There is often more than one way to skin a cat. If I understand what

you are trying to do with polynomials I think I have already

explained what you need to do to square a() and given you code to do

it. If I don't understand, perhaps you can explain better?

BTW, when you use Google Groups to post in newsgroups you need to fix

your quoted lines. Google Groups adds blank lines between the lines

of the quoted material and after a couple of quotes becomes

unreadable.

It is a bit confusing to me. Can I have your email id please? I can

send you a relevant paper for the circuit with the algorithm. May

be you will be able to understand it. I am unable to find more

information related to it.

vector_s: for i in 0 to 80 generate s(2*i)<= a(i); s(2*i + 1)<=

a(i+82); end generate; s(162)<= a(81);

Do you understand what this code is doing? It is generating the

signal s() from the signal a(). Is that clear?

vector_t1: for j in 0 to 6 generate t(j)<= '0'; end generate;

t(7)<= a(82); vector_t2: for i in 4 to 80 generate t(2*i)<=

a(i+7; t(2*i + 1)<= a(i+79); end generate; t(162)<= a(159);

This code generates t() from a().

For a 163-bit circuit, especially I do not understand this part. So

please help me out. Thanks!

I don't get it either. What are a(), s(), t() and z()? Is this

supposed to be squaring a() to get z()? If so, why is a() the same

length as z()? I can't find any of this code using Google.

I got your other email which was largely the same as your earlier

post I think. I prefer to discuss this here. There may be others

who would like to understand this or who can explain it. In fact,

you might try explaining what you are doing and ask how to do this in

other groups such as comp.dsp. Working from an undocumented code

section is not a great way to understand an algorithm.

I can't tell you anything about the code you posted. I have no idea

why they are doing all the calculations they are doing. I can read

the VHDL, but I can't read the mind of the person who wrote it.

I might be able to help you figure this out if you give more

background. What are you trying to do? What is the bigger picture?

There is often more than one way to skin a cat. If I understand what

you are trying to do with polynomials I think I have already

explained what you need to do to square a() and given you code to do

it. If I don't understand, perhaps you can explain better?

BTW, when you use Google Groups to post in newsgroups you need to fix

your quoted lines. Google Groups adds blank lines between the lines

of the quoted material and after a couple of quotes becomes

unreadable.

Agreed re Google!

This all looks like polynomials to me which are an art in themselves.

Without the writers intention it feels we're going to remain in the dark.

I confess that whenever I've need a polynomial to calculate or check a

CRC, I've used this rather invaluable site:

http://www.easics.be/webtools/crctool

Perhaps this might give Lokesh some insight?

elektroda.net NewsGroups Forum Index - VHDL Language - **Squaring of a binary number**