Spice simulation of IBIS details - model examples

Mon Mar 01, 2010 10:17 am   

As a simple exercise, I looked at the info in a IBIS file, which is
quite simple :
V-I tables, and pF and nS values for ramps.

So if you have a simple problem : What clock edge should I finally
get ?, you
can create a napkin Spice model, that can be used to track bench
tests.

The V-I tables can give the output impedance. For overshoot, use the N-
CH values, and for min-slew checks, use the (usually slightly higher)
P-CH values.

Slew values are used to set the PWL source, and R/C values here I have
split in two, and modeled, with a third C/2 for trace/load
capacitance..

example for a 30 ohm, 10pF and 1ns or 2ns ramp values 22nH parasitic
L.
This has two instances to show slew-range effects on one plot.

It is also small enough to easily fit inside most demo-mode Spice's
[ Tested on B2spice / LTSpice / SpiceOpus. ]

-jg

~~~~~~~~ Edited to be more human-understood ~~~~~~~

***** main circuit
V1 1 0 PWL ( 0 0
+ 50n 0
+ 52n 3.3
+ 100n 3.3
+ 102n 0)
R1 1 2 15
C1 2 0 5p
R2 2 3 15
C2 3 0 5p
L1 3 4 22n
C3 4 0 5p
IV2ns 4 0 0

V2 5 0 PWL ( 0 0
+ 50n 0
+ 51n 3.3
+ 100n 3.3
+ 101n 0)
R3 5 6 15
C4 6 0 5p
R4 6 7 15
C5 7 0 5p
L2 7 8 22n
C6 8 0 5p
IV1ns 8 0 0

..TRAN 1E-9 1.2E-7 3E-8 1E-9

..OPTIONS temp = 27
..end


~~~~~~~~~~~~~ LTSpice, B2Spice ~~~~~~~~~~

* IBIS_Check.cir for LTSpice
*

***** main circuit
V1 1 0 PWL ( 0 0
+ 50n 0
+ 52n 3.3
+ 100n 3.3
+ 102n 0)
R1 1 2 15
C1 2 0 5p
R2 2 3 15
C2 3 0 5p
L1 3 4 22n
C3 4 0 5p
IV2ns 4 0 0

V2 5 0 PWL ( 0 0
+ 50n 0
+ 51n 3.3
+ 100n 3.3
+ 101n 0)
R3 5 6 15
C4 6 0 5p
R4 6 7 15
C5 7 0 5p
L2 7 8 22n
C6 8 0 5p
IV1ns 8 0 0


..TRAN 1E-9 1.2E-7 3E-8 1E-9

* PickVisibleTraces V( V(4) then File.SavePlotSettings

..end

http://www.spiceopus.si/download/downloadw.html

~~~~~~~~~~~~~ SpiceOpus ~~~~~~~~~~~~~~~~
* IBIS_Check.cir for SpiceOpus
*

***** main circuit
V1 1 0 PWL ( 0 0
+ 50n 0
+ 52n 3.3
+ 100n 3.3
+ 102n 0)
R1 1 2 15
C1 2 0 5p
R2 2 3 15
C2 3 0 5p
L1 3 4 22n
C3 4 0 5p
IV2ns 4 0 0

V2 5 0 PWL ( 0 0
+ 50n 0
+ 51n 3.3
+ 100n 3.3
+ 101n 0)
R3 5 6 15
C4 6 0 5p
R4 6 7 15
C5 7 0 5p
L2 7 8 22n
C6 8 0 5p
IV1ns 8 0 0

* SpiceOpus script control section follows .control, this section is
less spice portable
..control
destroy all
tran 1E-9 1.2E-7 3E-8 1E-9
* was .TRAN 1E-9 1.2E-7 3E-8 1E-9
run
rusage time
setplot
setplot tran
plot v( v(4) xlabel t[s] ylabel '1nS Rise(r), 2nS Rise(g)'
..endc

..end

Mon Mar 01, 2010 10:30 am   

On 03/01/2010 12:17 AM, -jg wrote:

I'm not sure if it is that straight forward. From

"The Development of Analog SPICE Behavioral Model Based on IBIS Model"
Ying Wang and Han Ngee Tan, Proceedings of the Ninth Great Lakes
Symposium on VLSI, (March 1999)
http://www.cecs.uci.edu/~papers/compendium94-03/papers/1999/glsvlsi99/pdffiles/glsvlsi99_101.pdf


I would recommend a read through of that paper if you want to make a
SPICE model based on IBIS data (it is only four pages long).

This paper is built on the methodology presented in this paper, which
gives a bit more info:

"Extraction of Transient Behavioral Model of Digital I/O Buffers from
IBIS" - by Peivand Tehrani, Yuzhe Chen and Jiayuan Fang, 46th IEEE
Electronic Components & Technology Conference (May 28-31, 1996)
http://www.sigrity.com/papers/ectc96/ectc96ibis.pdf

Jared Casper

Mon Mar 01, 2010 12:05 pm   

On Mar 1, 10:30 pm, Jared Casper <jaredcas...@gmail.com> wrote:

Yup, which is why the spice model I have, is not using just R.
It also includes these AC parameters

a) Slew rate value
b) Capacitance
c) Inductance

-jg

Tue Mar 02, 2010 1:56 am   

On Mar 1, 4:30 am, Jared Casper <jaredcas...@gmail.com> wrote:

I can attest to the fact that there are things going on that are very
different from the static conditions. I ran an IBIS simulation on the
file provided by the vendor... actually, I don't thin it was a
simulation as much as just a display of the waveform shown in the IBIS
file. It clearly shows a quick rise time (~1 ns) to a level lower
than Vdd because of the 100 ohm load to ground. But after about 2-3
ns the voltage drops off and remains constant for the duration of the
20 ns data sample. I am pretty sure you can't generate this waveform
with a simple RLC model. It also makes me suspicious of the entire
IBIS file thing. It just seems like this is a very poor way to model
an I/O, but then I haven't looked at it in detail. I do know that the
one time I used a simulator, it did not give results so much like what
we measured. It predicted severe overshoot on the bus lines and we
observed very little.

Rick

Tue Mar 02, 2010 2:11 am   

On Mar 2, 12:56 pm, rickman <gnu...@gmail.com> wrote:

Yes, that sounds simply broken. Like the sim-engine,
and the model got out of step.
Did your scope 'reality check' look anything like that?


IBIS is simplified output from the 'real spice'.
So they just have single numbers for ramp rates, and
a table plot for I-V.

Given the limits of the information in the IBIS, you should still be
able to get useful spice data points.
Certainly more than enough, to correlate with bench measurements, and
for clock ringing (which is what you were looking for).

Tho I'm not sure I'd try and get Eye patterns from it
It's best to use Hyperlynx for that level of analysis.

Those spice examples look quite plausible to me.
Both show ringing, but with (expected) quite different amplitudes and
phases.

Tue Mar 02, 2010 2:44 am   

On Mar 1, 7:11 pm, -jg <jim.granvi...@gmail.com> wrote:

The "sim-engine" is just a display of the contents of the V-t curve
given in the model. I found it in the file and the data is exactly
like the curve drawn.



What the heck do you feed into Hyperlynx? That is what the IBIS
models are supposed to be for from what I have read. Hyperlynx is not
spice, it uses the IBIS models for the drivers and inputs and it gets
info on your pcb from your layout package. All in all, it is a *very*
expensive way to design high speed PCBs and like I said, I didn't find
it produced very good results.



In the end we picked a 12 mA, FAST output which gives a 6 ns rise time
with a small wiggle in the rising edge at around 2.6 volts pretty well
above the typical threshold. With an 8 mA drive the rise time is
slower and the wiggle shows up further down in the curve near the
threshold. The common factor is a ~4 ns time delay which matches the
end of the initial pulse in the V-t curve data. I don't think any of
this is ringing due to reflections in the trace. A 6 ns rise time
would require a trace a foot or more long to create any noticeable
reflection. The trace on this board is maybe 3 inches long total. I
don't know what the IBIS data is about.

Rick

Tue Mar 02, 2010 3:33 am   

On Mar 2, 1:44 pm, rickman <gnu...@gmail.com> wrote:

The top end Hyperlynx products, include the trace parasitics, and
lossy transmission line models. So if you are serious about eye
patterns, they are a good idea.
If you just want ringing/drive selector, then yes, they could be an
overkill.

Hence the spice alternative.



I used 22nH, and 5pF as the load, and got noticable ringing effects,
with fast-ish edges.

That ~3 inch trace will be 30-40nH, and rather more than 5pF, so your
slower edges should give similar results.

Try it and see :)

-jg

Tue Mar 02, 2010 7:15 am   

On Mar 1, 8:37 pm, -jg <jim.granvi...@gmail.com> wrote:

I'm talking about the boards. I get virtually no ringing with the
slower edge rates. The fastest, 20 mA/FAST, setting gives pronounced
ringing and 16 mA has some as well. They are both 2 ns or less rise
times. At 12 ns the ringing is gone and I only see the tiny notch in
the rising edge that I am convinced is not ringing or reflection.
BTW, a transmission line does not ring. You can get reflections, but
unless there is some sort of feedback in your IO driver that is
oscillating, you won't see true ringing with a transmission line...
unless there is something with transmission lines that I didn't
learn. It is often that reflections look like ringing because they
echo several times at lower amplitude each time around. No?

Rick

Tue Mar 02, 2010 8:08 am   

On Mar 2, 6:15 pm, rickman <gnu...@gmail.com> wrote:

It depends on your terminology.
The notch I mention below, I would call ringing, as it
comes from a LCR+Slope model. It is effectively ringing summed onto
the slowish rise time, and is not huge, but large enough to see a
slight reverse in voltage.


Just for fun, I added some guestimate numbers from what you said, and
added a probe to the driving end, and voila, guess what?

A small notch appears, on the driving end ;)

Which end were you probing, your end, or connector, or the customers
FPGA pin ?

-jg

Tue Mar 02, 2010 11:37 am   

rickman wrote:


Hyperlynx also can use spice (hspice or eldo) models, so you can use a
mixture of ibis and spice models for the simulation. And I think also
AMS and IBIS-AMI is supported.

And also the trace models do not have to come from the layout. I have
used the tool often for design exploration. For example checking the
termination schemes (ODT vs. separate resistors etc.) and the results
have matched quite well to the real world. Altough the trace was only
based on PCB stackup model, vias and trace lengths on different layers.

--Kim

Tue Mar 02, 2010 3:07 pm   

On Mar 2, 1:08 am, -jg <jim.granvi...@gmail.com> wrote:

The driver. Does it show up at the same time for both 8 and 12 mA
drive?

Rick

Tue Mar 02, 2010 9:25 pm   

On Mar 3, 2:07 am, rickman <gnu...@gmail.com> wrote:

That would be by varying the slew rate in the PWL source, and yes, it
comes and goes as the slew rate hits a critical threshold.

Spice says the waveform at the receive end does not have that notch.

-jg