Andrew Holme
Guest
Sun Mar 07, 2010 2:37 pm
What's the minimum clock pulse width I can drive into a Spartan 3 global
clock input via LVDS? I'm using the -5 speed grade device with VDDC cranked
up to 1.25V. I've currently got it working at 200 MHz ~ 50% duty = 2.5ns
pulses; but I want to lower the duty cycle. Can I squeeze the pulses to
below 2ns? I can't test this without re-spinning my board. I see
sub-nanosecond minimum clock widths and 720 MHz maximum toggle rates in the
datasheet; but I also see max 10pF input capacitance. 50% duty cycle keeps
the swing centred on VCM; but I lose that advantage with my low duty cycle.
I still reckon it should work; but it would be good to hear from others
who've pushed these limits.
TIA
Nico Coesel
Guest
Sun Mar 07, 2010 3:13 pm
"Andrew Holme" <ah_at_nospam.com> wrote:
Quote:
What's the minimum clock pulse width I can drive into a Spartan 3 global
clock input via LVDS? I'm using the -5 speed grade device with VDDC cranked
up to 1.25V. I've currently got it working at 200 MHz ~ 50% duty = 2.5ns
pulses; but I want to lower the duty cycle. Can I squeeze the pulses to
below 2ns? I can't test this without re-spinning my board. I see
sub-nanosecond minimum clock widths and 720 MHz maximum toggle rates in the
datasheet; but I also see max 10pF input capacitance. 50% duty cycle keeps
the swing centred on VCM; but I lose that advantage with my low duty cycle.
I still reckon it should work; but it would be good to hear from others
who've pushed these limits.
Isn't there a duty cycle limit in the datasheets? I did have some
problems driving a 100MHz clock at CMOS level into a Spartan 3. It
turned out the duty cycle was around 30% because the driver couldn't
handle 100MHz.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico_at_nctdevpuntnl (punt=.)
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