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Slightly OT: Digital watch circuits

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rickman
Guest

Tue Jan 03, 2017 5:44 am   



On 1/2/2017 9:35 AM, Theo Markettos wrote:
Quote:
Tim Wescott <tim_at_seemywebsite.com> wrote:
Seven FF _per digit_. I'm more interested in what was done back in the
day. Do you know how long the 4-bit CPU has been used?

The advert for one of the first (Sinclair Black Watch, 1975) describes the
chip:

quote
The chip...
The heart of the Black Watch is a unique IC designed by Sinclair and Custom
-built for them using state -of- the -art technology - integrated injection
logic. This chip of silicon measures only 3 mm x 3 mm and contains over
2000 transistors.The circuit includes
a) reference oscillator
b) divider chain
c) decoder circuits
d) display inhibit circuits
e) display driving circuits.
The chip is totally designed and manufactured in the UK, and is
the first design to incorporate all circuitry for a digital watch on a
single chip.

...and how it works
A crystal -controlled reference is used to
drive a chain of 15 binary dividers which reduce the frequency from 32,768
Hz to 1 Hz.This accurate signal is then counted into units of seconds,
minutes, and hours, and on request the stored information is processed by
the decoders and display drivers to feed the four 7- segment LED displays.
When the display is not in operation, special power- saving circuits on the
chip reduce current consumption to only a few microamps.
/quote

http://www.americanradiohistory.com/Archive-Practical/Wireless/70s/PW-1976-03.pdf
page 68
(fab was supposed to be Mullard but they pulled out, I think it was
eventually ITT)


Good find!

--

Rick C

Tim Wescott
Guest

Tue Jan 03, 2017 6:04 am   



On Mon, 02 Jan 2017 14:57:03 -0700, BobH wrote:

Quote:
On 01/02/2017 11:02 AM, Tim Wescott wrote:
On Mon, 02 Jan 2017 08:07:39 -0700, BobH wrote:

On 12/30/2016 02:03 PM, Tim Wescott wrote:
Someone on reddit asked about quartz watches, and I told them that
one

snip

It would be possible to implement a state machine that counts in 7
segment format, but it would be ugly to do, and probably larger than
simple ripple counters feeding into a shared bcd to 7 segment decoder.

That answers that question, except for the residual "probably".

Sprechen Sie Verilog? Give it a try.

I have done a lot of state machine design through the years and I can't
imagine why a 7 segment counting state machine would not be larger than
a simple ripple binary counter. I put the "probably" in because this is
usenet, and the probability of getting in a flame war over something
like this seems pretty high.

If you think about it, the muxed display implementation, with 3 bcd
ripple counters sharing one bcd to 7 segment decoder should be way
smaller than 4 7 bit counters with complex next state logic.


I'm really more a systems egghead with solid software (and, oddly, analog
circuit) design skills. I don't do much FPGA work, and what I end up
doing is nothing to write home about -- I generally know what's possible
in pure digital-land, and can work with the real logic guys to make it
happen.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

I'm looking for work -- see my website!

rickman
Guest

Tue Jan 03, 2017 8:30 am   



On 1/2/2017 6:04 PM, Tim Wescott wrote:
Quote:
On Mon, 02 Jan 2017 14:57:03 -0700, BobH wrote:

On 01/02/2017 11:02 AM, Tim Wescott wrote:
On Mon, 02 Jan 2017 08:07:39 -0700, BobH wrote:

On 12/30/2016 02:03 PM, Tim Wescott wrote:
Someone on reddit asked about quartz watches, and I told them that
one

snip

It would be possible to implement a state machine that counts in 7
segment format, but it would be ugly to do, and probably larger than
simple ripple counters feeding into a shared bcd to 7 segment decoder.

That answers that question, except for the residual "probably".

Sprechen Sie Verilog? Give it a try.

I have done a lot of state machine design through the years and I can't
imagine why a 7 segment counting state machine would not be larger than
a simple ripple binary counter. I put the "probably" in because this is
usenet, and the probability of getting in a flame war over something
like this seems pretty high.

If you think about it, the muxed display implementation, with 3 bcd
ripple counters sharing one bcd to 7 segment decoder should be way
smaller than 4 7 bit counters with complex next state logic.

I'm really more a systems egghead with solid software (and, oddly, analog
circuit) design skills. I don't do much FPGA work, and what I end up
doing is nothing to write home about -- I generally know what's possible
in pure digital-land, and can work with the real logic guys to make it
happen.


I don't know directly wiring 7 FFs for each digit is a horrible idea.
That would be coded as a FSM by connecting present states with next
states...

SUBTYPE DigitType is unsigned(6 downto 0);

CONSTANT DigitZero : DigitType := "0111111"
CONSTANT DigitOne : DigitType := "0000110"
CONSTANT DigitTwo : DigitType := "1011011"
CONSTANT DigitThree : DigitType := "1001111"
CONSTANT DigitFour : DigitType := "1100110"
CONSTANT DigitFive : DigitType := "1101101"
CONSTANT DigitSix : DigitType := "1111101"
CONSTANT DigitSeven : DigitType := "0000111"
CONSTANT DigitEight : DigitType := "1111111"
CONSTANT DigitNine : DigitType := "1100111"

SIGNAL DigitCur : DigitType;
SIGNAL CntEnable : std_logic;

PROCESS (clk, rst) BEGIN
IF (rst) THEN
DigitCur <= DigitZero ;
ELSIF rising_edge(clk) THEN
IF (CntEnable) THEN
case DigitCur is
when DigitZero => DigitCur <= DigitOne;
when DigitOne => DigitCur <= DigitTwo;
when DigitTwo => DigitCur <= DigitThree;
when DigitThree => DigitCur <= DigitFour;
when DigitFour => DigitCur <= DigitFive;
when DigitFive => DigitCur <= DigitSix;
when DigitSix => DigitCur <= DigitSeven;
when DigitSeven => DigitCur <= DigitEight;
when DigitEight => DigitCur <= DigitNine;
when DigitNine => DigitCur <= DigitZero;
when others => DigitCur <= DigitZero;
end case;
END IF;
END IF;
END PROCESS;

I recall coding a 7 seg to decimal decoder in software once and you
don't even need all the bits as input to determine the next state. I
think I used five. The above code ends up being 7 independent FSM, one
for each bit dependent on what ever ends up being minimal. So I don't
think the logic is very complex. The only real complexity is using 7
FFs instead of 4. A FF has some dozen or more gates and I expect the
PS->NS random logic is less that that for each bit.

For example, the bit for the 'a' segment, the one at the top of the
digit, is only a zero for the 1 and the 4. The preceding states are 0
and 3. To decode those two you can xor segments f and g, then and with
segment c and invert. a_next := not (c and (f_cur xor g_cur)) That's
pretty simple function, one 4 input LUT.

So maybe directly coding the digits with a 7 bit FSM is not such a bad
idea.

--

Rick C

Kevin Neilson
Guest

Tue Jan 03, 2017 9:51 pm   



Quote:

Wow. I think that 2000 transistors is less than half the way to a 4-bit
micro, isn't it? So maybe they went that way early on.

I'm sure they must've used a custom circuit initially. The text about the "display inhibit" circuit reminded me that the original digital watches were luminous (not LCD) and you had to push a button to display the time, in order to save the battery.


It would be an interesting homework problem to design a digital watch chip with the fewest 2-input gates. Gated clocks, glitches, and latches all allowed.

GaborSzakacs
Guest

Wed Jan 04, 2017 4:07 am   



Kevin Neilson wrote:
Quote:
Wow. I think that 2000 transistors is less than half the way to a 4-bit
micro, isn't it? So maybe they went that way early on.

I'm sure they must've used a custom circuit initially. The text about the "display inhibit" circuit reminded me that the original digital watches were luminous (not LCD) and you had to push a button to display the time, in order to save the battery.

It would be an interesting homework problem to design a digital watch chip with the fewest 2-input gates. Gated clocks, glitches, and latches all allowed.


Check out this article comparing the first Pulsar digital watch
to the new Apple watch:

https://dealspotr.com/article/apple-watch-has-come-a-long-way-since-the-first-digital-watch

It seems that this model (produced only in small quantity) did not have
a custom chip (article quotes 25 chips in the watch). It had a button
to illuminate the display and two magnet-activated switches to set the
time (hours and minutes). Modern digital alarm clocks still use the
same clunky Hour and Minute buttons to set time, which is very
frustrating when you want to move the time back by one minute or one
hour.

A friend of mine worked at Fairchild not long after the first digital
watches came out. He told me that they made chips for digital clocks
that included a 4-bit micro. Chips for AC plug-in clocks used 60 Hz
from the power mains for the time base, with a self-calibrated (against
the power mains frequency) internal oscillator for battery-backup mode.


--
Gabor

Theo Markettos
Guest

Wed Jan 04, 2017 8:48 pm   



GaborSzakacs <gabor_at_alacron.com> wrote:
Quote:
It seems that this model (produced only in small quantity) did not have
a custom chip (article quotes 25 chips in the watch). It had a button
to illuminate the display and two magnet-activated switches to set the
time (hours and minutes). Modern digital alarm clocks still use the
same clunky Hour and Minute buttons to set time, which is very
frustrating when you want to move the time back by one minute or one
hour.


There's some pictures of the mechanism here:
http://www.timetrafficker.com/private/pulsar-p1-25-chip-module/

What's interesting is the modern-looking SMD construction, with gold tracks
on a ceramic substrate. The LEDs use discrete bond wires but all the chips
are in 12/14 pin ceramic packages, of roughly MSOP size.

Each of the 25 chips is lettered. There are 5 As, 5 Ks, 5 Gs, 3 Cs, and one
each of BDEFHIL - looking at the layout it's possible to infer something
about their function.

I wonder if they're 74- or more likely 4000-series in custom packages?

Theo

Kevin Neilson
Guest

Fri Jan 06, 2017 12:16 am   



Quote:

There's some pictures of the mechanism here:
http://www.timetrafficker.com/private/pulsar-p1-25-chip-module/


I was wondering what the glass tubes underneath the circuit board were--they look like the inside of reed relays. Then I realized that's exactly what they are. They're the switches used for setting the time, activated with an external magnet.

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