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Single process style with Xilinx

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Mike Treseler
Guest

Fri Jan 22, 2010 12:42 am   



adamk wrote:

Quote:
template_v_rst: 46 FF 97 LUT
template_s_rst: 54 FF 100 LUT
my changed template: 45 FF 100 LUT

They all pass the sim.
As far as i can tell the extra registers on the outputs don't get
removed in template_s_rst.

Since it passes sim, I assume you mean duplicates like this:

A--[dq]--B_v---[dq]--B---[..feedback.]
\----[dq]------------------------> B_q [port]


Quote:
What's baffling me is that for my design tempate_s_rst and my modified
one both behaviourly sim the same but for a gate sim template_s_rst is
different and fails while the modified one passes and looks the same
as the behioural sim.

Maybe yours it better.

For the synchronous reset case, you might want
to wrap the design with input and output flops
to make valid comparisons.

-- Mike T

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