stefimkert
Guest
Mon Jul 24, 2006 8:07 am
How can I prevent the getting single bit busses as [0:0] in my verilog
netlist? I want just "wires" (std_logic's instead of
std_logic_vectors):
module lpesram(clk, d, q);
input clk;
input [0:0] d;
output [0:0] q;
wire [0:0] d;
wire [0:0] q;
...
endmodule
PS: I'm using DC 2005.09
Alvin Andries
Guest
Wed Jul 26, 2006 5:27 pm
"stefimkert" <stefimke_at_gmail.com> wrote in message
news:1153728439.979995.253450_at_m79g2000cwm.googlegroups.com...
Quote:
How can I prevent the getting single bit busses as [0:0] in my verilog
netlist? I want just "wires" (std_logic's instead of
std_logic_vectors):
module lpesram(clk, d, q);
input clk;
input [0:0] d;
output [0:0] q;
wire [0:0] d;
wire [0:0] q;
...
endmodule
PS: I'm using DC 2005.09
What's in the source code? std_logic_vector(0 [down]to 0) would result into
the [0:0] that you see.
Regards,
Alvin.
