simulation limit

Mon Dec 07, 2009 9:19 am   

Hi all,

I have a query regarding to the post route simulation(timing
simulation) using Modelsim, presently i am using 6.4 PE.
In first i am done Functional simulation using VHDL test bench
implementation, and when "End of Test" assertion reached and
simulator will stop from assertion Failure condition; now i got let
say end time of simulation is 10 us.

Now loaded necessary files to run timing simulation; now i want to
know how to decide to give end of simulation time to run; where as
this timing simulation will take account all the gates, paths
etc..delays. so appending on the time from where i got functional
simulation is fine or need to have some analysis? To give end run time
simulation.

Please give some exposure on this issue..

Mon Dec 07, 2009 6:40 pm   

JSreeniv wrote:


If I use the same testbench, the sim time is the same
but the coffee drinking time may be ten times longer.

By the way, a gate sim is a test of your
tools, rules and testbench, not your design.

-- Mike Treseler

Mon Dec 07, 2009 9:56 pm   

I too use the same simulation run times. Just to clarify
something that Mike said:


One set of rules are coding style rules. If you violate
coding style rules, your gate design will have issues that
are not able to be identified in RTL simulations.

For example,
Y <= A after 20 ns ;

If your clock period is 10 ns, this simulates in a similar
fashion to two flip-flops. However, in synthesis, no
hardware will be created for after, so your gate simulations
will differ from your RTL sims.

Best,
Jim
SynthWorks

Tue Dec 08, 2009 8:52 am   

On 7 Dez., 18:40, Mike Treseler <mtrese...@gmail.com> wrote:

You should add your skill in using this tools .
Too often happens that simualtion shows an error made in timing
analysis not by tool but by developer.

regards Thomas