Daku
Guest
Wed Jul 14, 2010 6:00 pm
Could some Verilog guru please help ? I am trying to simulate the
resolution sub-layer of
the recently proposed new 802.3ba standard.
The IEEE draft document states:
"The OUTPUT_UNIT parameter can take one of three values ONE, ZERO or
DATA_COMPLETE. It represents a single data bit. The DATA_COMPLETE
value signifies that the Media Access Control layer has no data to
output"
So, if we represent ONE as 1b'1, ZERO as 1b'0, how are we to represent
DATA_COMPLETE - high impedance value maybe ?
Any hints, suggestions would be of great help - thanks in advance.
Muzaffer Kal
Guest
Wed Jul 14, 2010 6:00 pm
On Wed, 14 Jul 2010 08:00:28 -0700 (PDT), Daku <dakupoto_at_gmail.com>
wrote:
Quote:
Could some Verilog guru please help ? I am trying to simulate the
resolution sub-layer of
the recently proposed new 802.3ba standard.
The IEEE draft document states:
"The OUTPUT_UNIT parameter can take one of three values ONE, ZERO or
DATA_COMPLETE. It represents a single data bit. The DATA_COMPLETE
value signifies that the Media Access Control layer has no data to
output"
So, if we represent ONE as 1b'1, ZERO as 1b'0, how are we to represent
DATA_COMPLETE - high impedance value maybe ?
No, you need another signal which denotes whether data_complete is
valid or not. The sentence " It represents a single data bit" means
that when there is actual data, it is only one bit; it doesn't mean
that the whole message can be implemented with a single signal (which
needs to have 3 values). You can implement in RTl with two wires, one
which carries the 'bit' and the other whether 'bit' is valid or not.
--
Muzaffer Kal
DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
