Signal Assignment in a Process

Sat May 29, 2010 10:18 am   

Hey guys. I need a second opinion regarding something stated in the book
I'm learning VHDL from. The book is "Circuit Design with VHDL" by Volnei
A. Pedroni. In it the author says the following (page 136):

"Generally, only one assignment to a SIGNAL is allowed within a PROCESS,
so the software will either consider only the last one (sel <= sel + 2 in
solution 1) or simply issue an error message and stop compilation."

Does this mean that someone is pushing their luck by assigning a default
value for a signal toward the beginning of the process and conditionally
reassigning it? For example:

process (CurState, D)
begin

NextState <= CurState; -- By default stay in the current state.

case CurState is

when stHolding =>
-- Stay in this state until D is asserted.
if (D = '1') then
NextState <= stNormal;
end if;

when stNormal =>
.
.
.
end case;
end process;

I was looking through the sample chapter from one of Pong P. Chu's books
and he uses the above scheme.

Is this something that isn't 'kosher' and is supported only by some
vendors or is this something that should be portable across all vendors?

Sat May 29, 2010 11:16 am   

On Sat, 29 May 2010 04:18:00 -0500, Wendigo <Wendigo_at_nowhere.org> wrote:


It means you need a better book.

Ashenden "Designer's Guide to VHDL" is still one of the best.

Later assignments will override earlier ones (therefore earlier ones are
a good pattern for settign defaults). But this is NOT an error and if
any tool stopped compilation for this, I would report it as a tool
fault.


It's a bad example, but for a different reason altogether.

Consider in the above, you introduce other inputs besides D; it is all
too easy to forget to add them to the sensitivity list. Now the
simulation and synth do different things...

The single process state machine is simpler, and far less likely to go
wrong during maintenance.

process (reset, clock)
-- No maintenance required on sensitivity lists...
begin

-- CurState <= CurState; -- By default stay in the current state.
-- Commented out because redundant in the single-process form

if rising_edge (clk) then
case CurState is
when stHolding =>
-- Stay in this state until D is asserted.
if (D = '1') then
CurState <= stNormal;
end if;

when stNormal =>
....

I have heard a lot of good things about the Pong Chu book, but if he
doesn't recommend the single process SM, I'm disappointed.

- Brian

Sat May 29, 2010 1:31 pm   

On Sat, 29 May 2010 11:16:44 +0100, Brian Drummond wrote:

<snip>

Thanks for the advice, Brian. I'll definitely look into getting a
another book. I'll take a look at Ashenden's book. Pedroni's book is
actually pretty good but it is always a good idea to have more than one
person's view on technical matters.

It's funny that you bring up the single process method of state machines.
I've been struggling a bit with the so-called dataflow method of coding (a
bunch of concurrent code and small processes.) I'm a software developer
so I find the single process method much easier to understand. I'm glad
that it is recommended by someone who knows what they're doing.

A couple of days ago I ran across a PDF prepared by Mike Treseler that
shows a single process template. It was a real god-send for me. It
looks like it is a good way to structure non-trivial VHDL code. It
will certainly make it much easier for *me* to write and understand.

Thanks again.

Sat May 29, 2010 1:55 pm   

On Sat, 29 May 2010 07:31:13 -0500, Wendigo wrote:


I just took a closer look at the PDF that I was referring to and it
references Mike Treseler's template. The document, I believe, was
prepared by someone else, however.

The document is here:

ens.ewi.tudelft.nl/Education/courses/et4351/structured_vhdl_2010.pdf

It also shows Jari Gaisler's two process scheme.

Sat May 29, 2010 10:02 pm   

Wendigo wrote:


That's a matter of opinion, but it works fine for me and
it is certainly no more dangerous than an asynchronous process.

I'm a big fan of python functions.
Single process entities let me do gates and flops, python style.


I didn't write it, but is an excellent collection
of vhdl synthesis styles found in the wild.

My examples are here:
http://mysite.verizon.net/miketreseler/
Sometimes I wonder if I'll have time
to write any more before I retire ;)

In any case, I'm glad to hear there are
other single-threaded bit bouncers out there ;)

Thanks for the pdf link. I never thought I would see a
single process entity in an academic document.

-- Mike Treseler

ens.ewi.tudelft.nl/Education/courses/et4351/structured_vhdl_2010.pdf

Sun May 30, 2010 6:47 am   

Thanks for the link to your examples, Mike. I'm going to start patterning
my code after your template.