EDAboard.com | EDAboard.de | EDAboard.co.uk | WTWH Media

sign extension in Verilog 2001

Ask a question - edaboard.com

elektroda.net NewsGroups Forum Index - Verilog Language - sign extension in Verilog 2001

Goto page Previous  1, 2

Rick C
Guest

Mon Apr 20, 2020 6:45 pm   



On Monday, April 20, 2020 at 12:24:50 PM UTC-4, Kevin Neilson wrote:
Quote:

In the second version, is the assignment to branchloc2_sgnext a regular concurrent statement or is this only executed during initialization?

branchloc2_sgnext is a continuous assignment so it is automatically updated whenever branchloc2 is.


Ok, I got it. I was thinking this was an assignment as part of a declaration like in VHDL. But this is a declaration which is part of a continuous assignment. I forgot you can do that in Verilog.


Quote:
In the third case w
hat size is an int in Verilog? Is it like VHDL, 32 bits by default? If cpupc were less than 32 bits would that be a problem? If cpupc were more than 32 bits would that be a problem?

I believe an 'int' is always 32 bits, so this case would probably not work if cpupc were bigger than 32 bits.


What would happen if cpupc were smaller than 32 bits? In VHDL the int has a range of a 32 bit word, but it's not really a 32 bit word... it's just an int. To add an int to a signed or unsigned it has to be converted (in the "+" definition) to a size matching the signed or unsigned.

It's unclear to me how ints are handled in Verilog.

--

Rick C.

--- Get 1,000 miles of free Supercharging
--- Tesla referral code - https://ts.la/richard11209

Kevin Neilson
Guest

Mon Apr 20, 2020 9:45 pm   



Quote:
What would happen if cpupc were smaller than 32 bits? In VHDL the int has a range of a 32 bit word, but it's not really a 32 bit word... it's just an int. To add an int to a signed or unsigned it has to be converted (in the "+" definition) to a size matching the signed or unsigned.

It's unclear to me how ints are handled in Verilog.

I think an 'int' is identical to a 32-bit signed reg. If cpupc were less than 32 bits, I don't think there would be a problem. The extra upper bits in the int will just be truncated. In Verilog, you can sum together things of different sizes with no conversions.


Rick C
Guest

Wed Apr 22, 2020 4:45 am   



On Monday, April 20, 2020 at 4:16:09 PM UTC-4, Kevin Neilson wrote:
Quote:
What would happen if cpupc were smaller than 32 bits? In VHDL the int has a range of a 32 bit word, but it's not really a 32 bit word... it's just an int. To add an int to a signed or unsigned it has to be converted (in the "+" definition) to a size matching the signed or unsigned.

It's unclear to me how ints are handled in Verilog.

I think an 'int' is identical to a 32-bit signed reg. If cpupc were less than 32 bits, I don't think there would be a problem. The extra upper bits in the int will just be truncated. In Verilog, you can sum together things of different sizes with no conversions.


Yeah, trouble is you have to know the details of what happens when it does that. What gets extended, what gets truncated and when it sign extends vs. zero padding. That's the sort of thing I expect to be noted in books on Verilog along with other "gotchas" and I'm told no one has written that.

Thanks for all the info. It has been educational.

--

Rick C.

--+ Get 1,000 miles of free Supercharging
--+ Tesla referral code - https://ts.la/richard11209

Goto page Previous  1, 2

elektroda.net NewsGroups Forum Index - Verilog Language - sign extension in Verilog 2001

Ask a question - edaboard.com

Arabic version Bulgarian version Catalan version Czech version Danish version German version Greek version English version Spanish version Finnish version French version Hindi version Croatian version Indonesian version Italian version Hebrew version Japanese version Korean version Lithuanian version Latvian version Dutch version Norwegian version Polish version Portuguese version Romanian version Russian version Slovak version Slovenian version Serbian version Swedish version Tagalog version Ukrainian version Vietnamese version Chinese version Turkish version
EDAboard.com map