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David Perry
Guest

Wed Jul 20, 2016 3:41 pm   



If I have a shared variable which is only ever written by one process, but could be read by multiple, will this generally work? Simulation gives me the correct results but I don't want to fall into any traps :)

If I don't do sequential operations on the variable such as:
a = b;
a = a + c; --result is b + c
then should I be using a signal? Is there any advantage to either method?


I've noticed that the simulation can't display variables (Xilinx ISim), only signals. Could this be because a signal has to be fully synthesised, but a variable can get optimised away to something that doesn't quite resemble the variable anymore? (I may be completely up the garden path with this).

David Perry
Guest

Wed Jul 20, 2016 5:30 pm   



Quote:
I know one advantage of using a signal. If you used a signal you would
not be asking about it.


I've used both, at the moment I'm not seeing an advantage either way.

Quote:
I've noticed that the simulation can't display variables (Xilinx ISim), only signals. Could this be because a signal has to be fully synthesised, but a variable can get optimised away to something that doesn't quite resemble the variable anymore? (I may be completely up the garden path with this).

Not so much "optimized away". Other than global variables, variables
don't exist between invocations of the code unit where they are defined.
This is not exactly true as using the value of a variable before
assigning it a value creates a latch or register.


I've yet to get my head around invocation. I have managed to steer clear of latches tho, yay!

Quote:
Maybe I'll try a few simulations to see if I can get a variable to show
in the waveform display.


The only way I've managed that is by shoving it to a signal.

> You can view the value of a variable in a watch window, right?

I didn't even know there was a watch window (I'm on ISE 14.6)

KJ
Guest

Wed Jul 20, 2016 5:55 pm   



On Wednesday, July 20, 2016 at 9:41:25 AM UTC-4, David Perry wrote:
Quote:
If I have a shared variable which is only ever written by one process, but
could be read by multiple, will this generally work? Simulation gives me
the correct results but I don't want to fall into any traps :)

If I don't do sequential operations on the variable such as:
a = b;
a = a + c; --result is b + c
then should I be using a signal? Is there any advantage to either method?


If you're only using this for simulation, then either method is OK. If you intend to synthesize this code, then you'll have to check to see if your synthesis tool supports shared variables. In theory, updating variables in simulation is quicker than signals (i.e. your wall clock time). You can experiment with both, but you'll probably be hard pressed to measure a significant difference unless this signal/variable gets updated a lot.

Quote:

I've noticed that the simulation can't display variables (Xilinx ISim),
only signals. Could this be because a signal has to be fully synthesised,
but a variable can get optimised away to something that doesn't quite
resemble the variable anymore? (I may be completely up the garden path
with this).


No, this is just a limitation of the simulation tool. I don't know about ISim, but with Modelsim, you can simply drag a variable over to the wave window for display. The drawback is there is no way to get the history so you will have to set it up at start of sim if you want it. With a signal you can log the activity to a file. Then if you want to display the signal in the wave window it will show the entire history from t=0. Again, this is Modelsim behavior, ISim may be different.

Kevin Jennings

Jim Lewis
Guest

Wed Jul 20, 2016 5:57 pm   



As of VHDL-2002, all shared variables shall be a protected type.

Yes some vendors support shared variables with regular types for RAMs. However, outside of modeling RAMs, I would not use shared variables with anything except a protected type.

Going further, OSVVM (see http://www.osvvm.org) offers a memory modeling package (MemoryPkg) based on protected types. It uses a sparse data structure internally. For larger RAM models, this can be a significant simulation time saver. It would be a big win to get FPGA vendors to support it.

Best,
Jim
jim at synthworks dot com

rickman
Guest

Wed Jul 20, 2016 9:01 pm   



On 7/20/2016 9:41 AM, David Perry wrote:
Quote:
If I have a shared variable which is only ever written by one process, but could be read by multiple, will this generally work? Simulation gives me the correct results but I don't want to fall into any traps :)

If I don't do sequential operations on the variable such as:
a = b;
a = a + c; --result is b + c
then should I be using a signal? Is there any advantage to either method?


I know one advantage of using a signal. If you used a signal you would
not be asking about it.


> I've noticed that the simulation can't display variables (Xilinx ISim), only signals. Could this be because a signal has to be fully synthesised, but a variable can get optimised away to something that doesn't quite resemble the variable anymore? (I may be completely up the garden path with this).

Not so much "optimized away". Other than global variables, variables
don't exist between invocations of the code unit where they are defined.
This is not exactly true as using the value of a variable before
assigning it a value creates a latch or register.

Maybe I'll try a few simulations to see if I can get a variable to show
in the waveform display.

You can view the value of a variable in a watch window, right?

--

Rick C

David Perry
Guest

Wed Jul 20, 2016 9:38 pm   



> If you're only using this for simulation, then either method is OK. If you intend to synthesize this code, then you'll have to check to see if your synthesis tool supports shared variables. In theory, updating variables in simulation is quicker than signals (i.e. your wall clock time). You can experiment with both, but you'll probably be hard pressed to measure a significant difference unless this signal/variable gets updated a lot.

I'm only at the simulation stage, I might have a go at building it into a small project and see if it compiles. I'm moving from schematic entry to vhdl, I'm used to the hardware result being the same as the simulation without the need to worry about synthesis, it generally 'just works' when it's compiles. I didn't actually realise it didn't synthesise it when it runs the simulation.

> No, this is just a limitation of the simulation tool. I don't know about ISim, but with Modelsim, you can simply drag a variable over to the wave window for display. The drawback is there is no way to get the history so you will have to set it up at start of sim if you want it. With a signal you can log the activity to a file. Then if you want to display the signal in the wave window it will show the entire history from t=0. Again, this is Modelsim behavior, ISim may be different.

ISim is pretty similar, but I get a warning that it doesn't support variables. I see the latest value in the waveform list, but no waveform.
If I really need to see it, I just signal<=variable as a temporary measure, so it's not so bad.

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