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Same syntax for variable and signal update

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elektroda.net NewsGroups Forum Index - VHDL Language - Same syntax for variable and signal update

Rob Gaddi
Guest

Fri Jun 09, 2017 9:25 pm   



So I'm writing code generating code and running into a thing that's
syntactically icky.

procedure UPDATE_REGISTER(
dat : in std_logic_vector;
variable reg: inout fancytype) is
begin
reg := UPDATE_FANCYDATA(dat, reg);
end procedure UPDATE_REGISTER;

procedure UPDATE_REGISTER_SIG(
dat : in std_logic_vector;
signal reg: inout fancytype) is
begin
reg <= UPDATE_FANCYDATA(dat, reg));
end procedure UPDATE_REGISTER_SIG;

As far as I understand it (and please someone correct me if I'm wrong)
those procedures need different definitions because I need to use the
current update semantics. And I need to use different names for them
even because you can't differentiate subprogram overloads by nothing but
class.

Does anyone have a better way of doing this? Ultimately this is going
to be working on single elements at a time of large composites, and so I
don't like the simulation performance implications of something like:

signal sreg : fancytype;
...
process:
variable vreg : fancytype;
begin
wait until rising_edge(clk);
vreg := sreg;
UPDATE_REGISTER(vreg);
sreg <= vreg;
end process;

Anyone have a more elegant solution?


--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

Jim Lewis
Guest

Thu Jun 22, 2017 1:17 am   



Hi Rob,
The function you implied with UPDATE_REGISTER seems to do it quite well.

For procedures, perhaps this is an update needed for VHDL-2020.
Know of anyone willing to write an LCS. :)

Did you post to stack overflow as well?

Jim

elektroda.net NewsGroups Forum Index - VHDL Language - Same syntax for variable and signal update

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