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Safe State Machine with Conditional when others

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Guest

Sat Jun 01, 2019 2:45 am   



Can you make a finite state machine with a when others clause that has a conditional statement inside? This would be for synthesizing a "safe case" state machine with Synplify Pro.

For example:

when others =>
if (a = ''1') then
next_state <= IDLE;
elsif (b = '1') then
next_state <= READ;
else
next_state <= ERROR;
end if;

I have never actually done this before before and have only seen simple "when others" with only a single state assignment.

KJ
Guest

Sat Jun 01, 2019 2:45 am   



Yes

HT-Lab
Guest

Sun Jun 02, 2019 3:45 pm   



On 01/06/2019 02:24, digitalguy33_at_gmail.com wrote:
Quote:
Can you make a finite state machine with a when others clause that has a conditional statement inside? This would be for synthesizing a "safe case" state machine with Synplify Pro.

For example:

when others =
if (a = ''1') then
next_state <= IDLE;
elsif (b = '1') then
next_state <= READ;
else
next_state <= ERROR;
end if;

I have never actually done this before before and have only seen simple "when others" with only a single state assignment.

You will find most synthesis tools (including Synplify Pro?) can do this
automatically for you, search your manual for safe FSM attribute. Some
HiRel tools used in the space industry will have the additional options
to add FEC to your FSM. This means that your FSM can either detect an
illegal state (and jump to a recovery state) or correct the illegal
state and continue as normal (assuming you don't to many bit flips in
the same clock cycle).

Regards,
Hans.
www.ht-lab.com

Thomas Stanka
Guest

Mon Jun 03, 2019 2:45 pm   



Am Samstag, 1. Juni 2019 03:24:32 UTC+2 schrieb digita...@gmail.com:
> I have never actually done this before before and have only seen simple "when others" with only a single state assignment.

I think the answer is obvious for you when you consider a simple fsm with all (2^n) states used.
In case you use enumerated types you could have a case with a branch for each state explicit as selector (eg case state1=>...case state4=>.. end case;), but you could also have the fourth state selected by others ("case others => do_all_state4_stuff()".)

In general you should not mix up the function of Synplify Pro for safe state and the others-part.
Synplify Pro detectes when an others-clause is never reached and optimizes those states regardless of your code.

There is no functional difference for Synplify between
type state_t is (idle, do1, do2)
..
case
idle => wait_and_goto_do1()
do1=> wait_and_goto_do2()
do2 => wait_and_goto_idle()
end case
and

type state_t is (idle, do1, do2, notused)
..
case
idle => wait_and_goto_do1()
do1=> wait_and_goto_do2()
do2 => wait_and_goto_idle()
others => goto_idle()
end case

The functionality of Safe-FSM-encoding is also not changed by those two code snipplets (for all those version of Synplify I tried up to now).

A real difference would be, if you would set the state "notused" as reset-value for the fsm as this ensures all four states are reachable and could not optimised away.

regards,

Thomas

Rick C
Guest

Wed Jun 05, 2019 12:45 am   



On Friday, May 31, 2019 at 9:24:32 PM UTC-4, digita...@gmail.com wrote:
Quote:
Can you make a finite state machine with a when others clause that has a conditional statement inside? This would be for synthesizing a "safe case" state machine with Synplify Pro.

For example:

when others =
if (a = ''1') then
next_state <= IDLE;
elsif (b = '1') then
next_state <= READ;
else
next_state <= ERROR;
end if;

I have never actually done this before before and have only seen simple "when others" with only a single state assignment.


I believe you are asking about coding a state machine in VHDL, not anything specific to Synplify Pro. A VHDL synthesis tool doesn't really know you are coding a state machine. It just sees the logic you are implementing and implements that logic in the technology of your target. So you can put any conditionals anywhere you want and the state machine will do exactly what you are specifying. The only problem is if your HDL is not really describing what you think it is. Then that is what simulation is for.

--

Rick C.

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