RTL Synthesis & SDF file

Wed Aug 29, 2007 10:01 pm   

What does SDF, and Back-annotation/Forward annotation mean? How is an
SDF File generated, and why is Gate Level simulation done?

Can someone explain how to do synthesis and what tools/file extensions
(.sdf, .lib etc) mean?

Thu Sep 13, 2007 4:04 pm   

LIB is technology library file and contains timing, power and area
characterization of the cells, but no geometry information. SDF is the
standard delay format. There are HDL simulation models of the cells as
well. SDF characterizes the delay parameters and back annotate to the
HDL simulation models, for logic level simulation with the delay
parasitics in the SDF.

Thanks,
Koustav


On Aug 29, 5:01 pm, "asic1...@gmail.com" <asic1...@gmail.com> wrote: