JohnSmith
Guest
Tue Sep 21, 2010 9:26 am
Hi,
I have this vhdl code for creating ROM. How could be in verilog?
architecture a of test is
-- ROM declaration
type t_array is array (0 to 63) of std_logic_vector(4 downto 0);
constant ROM :
t_array :=("10001","10010","10100","10101","10110","11000","11001","11010",
"11011","11100","11101","11110","11110","11111","11111","11111",
"11111","11111","11111","11110","11110","11101","11100","11011",
"11010","11001","11000","10110","10101","10100","10010","10001",
"01111","01110","01100","01011","01010","01000","00111","00110",
"00101","00100","00011","00010","00010","00001","00001","00001",
"00001","00001","00001","00010","00010","00011","00100","00101",
"00110","00111","01000","01010","01011","01100","01110","01111");
Thanks
gabor
Guest
Thu Sep 23, 2010 4:55 pm
On Sep 21, 2:26 am, JohnSmith <csnew...@gmail.com> wrote:
Quote:
Hi,
I have this vhdl code for creating ROM. How could be in verilog?
architecture a of test is
-- ROM declaration
type t_array is array (0 to 63) of std_logic_vector(4 downto 0);
constant ROM :
t_array :=("10001","10010","10100","10101","10110","11000","11001","11010",
"11011","11100","11101","11110","11110","11111","11111","11111",
"11111","11111","11111","11110","11110","11101","11100","11011",
"11010","11001","11000","10110","10101","10100","10010","10001",
"01111","01110","01100","01011","01010","01000","00111","00110",
"00101","00100","00011","00010","00010","00001","00001","00001",
"00001","00001","00001","00010","00010","00011","00100","00101",
"00110","00111","01000","01010","01011","01100","01110","01111");
Thanks
I expected Jonathan Bromley to jump in on this one, since he's the
VHDL / Verilog guru. But I'll give it a shot. Usually when I
make a ROM in Verilog I don't place the ROM contents in the source
code, but rather in a separate hex or binary file that gets read in
like:
wire [4:0] ROM [0:63];
integer i;
initial begin
$readmemb ("ROM.txt",ROM);
end
And the contents of the ASCII file ROM.txt would look like
10001 10010 10100 10101 10110 11000 11001 11010
11011 11100 11101 11110 11110 11111 11111 11111
11111 11111 11111 11110 11110 11101 11100 11011
11010 11001 11000 10110 10101 10100 10010 10001
01111 01110 01100 01011 01010 01000 00111 00110
00101 00100 00011 00010 00010 00001 00001 00001
00001 00001 00001 00010 00010 00011 00100 00101
00110 00111 01000 01010 01011 01100 01110 01111
If I do this for Xilinx XST, I would place each
value in the ROM.txt file on a separate line, because
XST has an issue with using a space as a delimiter.
Regards,
Gabor
glen herrmannsfeldt
Guest
Thu Sep 23, 2010 8:16 pm
gabor <gabor_at_alacron.com> wrote:
(snip, someone wrote)
Quote:
I have this vhdl code for creating ROM. How could be in verilog?
(snip)
Quote:
I expected Jonathan Bromley to jump in on this one, since he's the
VHDL / Verilog guru. But I'll give it a shot. Usually when I
make a ROM in Verilog I don't place the ROM contents in the source
code, but rather in a separate hex or binary file that gets read in
like:
wire [4:0] ROM [0:63];
integer i;
initial begin
$readmemb ("ROM.txt",ROM);
end
I believe that is a common way to do it.
Otherwise, as far as I know, it is done with CASE.
A little more typing needed than for VHDL, unusual for verilog.
-- glen
Cary R.
Guest
Thu Sep 23, 2010 9:07 pm
On 9/23/2010 12:42 PM, gabor wrote:
Quote:
In C, when you define an array you can initialize it with a list in
curly braces like:
int foo[] = {1, 2, 3, 4, 5};
I would have expected something similar for Verilog, but didn't
run into it.
As for having the data in a separate file, I find it generally
easier to work with, since often the ROM contents are generated
from some other application and it is a pain to reformat it
and then paste (or `include) it into a Verilog source. It
would be nice to have a similar syntax for initializing short
arrays, however.
SystemVerilog or should I say the new Verilog does support array
initialization.
Cary
gabor
Guest
Thu Sep 23, 2010 10:42 pm
On Sep 23, 1:16 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
Quote:
gabor <ga...@alacron.com> wrote:
(snip, someone wrote)
I have this vhdl code for creating ROM. How could be in verilog?
(snip)
I expected Jonathan Bromley to jump in on this one, since he's the
VHDL / Verilog guru. But I'll give it a shot. Usually when I
make a ROM in Verilog I don't place the ROM contents in the source
code, but rather in a separate hex or binary file that gets read in
like:
wire [4:0] ROM [0:63];
integer i;
initial begin
$readmemb ("ROM.txt",ROM);
end
I believe that is a common way to do it.
Otherwise, as far as I know, it is done with CASE.
A little more typing needed than for VHDL, unusual for verilog.
-- glen
In C, when you define an array you can initialize it with a list in
curly braces like:
int foo[] = {1, 2, 3, 4, 5};
I would have expected something similar for Verilog, but didn't
run into it.
As for having the data in a separate file, I find it generally
easier to work with, since often the ROM contents are generated
from some other application and it is a pain to reformat it
and then paste (or `include) it into a Verilog source. It
would be nice to have a similar syntax for initializing short
arrays, however.
Regards,
Gabor
glen herrmannsfeldt
Guest
Thu Sep 23, 2010 11:30 pm
gabor <gabor_at_alacron.com> wrote:
Quote:
(snip, someone wrote)
I have this vhdl code for creating ROM. How could be in verilog?
(snip, I wrote)
Quote:
Otherwise, as far as I know, it is done with CASE.
A little more typing needed than for VHDL, unusual for verilog.
In C, when you define an array you can initialize it with a list in
curly braces like:
int foo[] = {1, 2, 3, 4, 5};
I would have expected something similar for Verilog, but didn't
run into it.
Yes, CASE isn't quite that compact, but works fine for the
smaller ROMs.
Quote:
As for having the data in a separate file, I find it generally
easier to work with, since often the ROM contents are generated
from some other application and it is a pain to reformat it
and then paste (or `include) it into a Verilog source. It
would be nice to have a similar syntax for initializing short
arrays, however.
I only noticed recently that it didn't exist in verilog,
and only with this thread that it did in VHDL.
For large ROMs, I like the separate file best.
Easy to generate, modify, and use with the verilog code.
-- glen
