rocketio TX delay between sata0 and sata1

Mon Feb 15, 2010 11:08 pm   

Hi, I'm workng with MGT as GT_CUSTOM.
I use the MGT for transmiting to pulses of .66ns(1/15Ghg).
I check all the delays with FPGA editor and all was ok, but I mesure th
pulses at the SATA conector and there are a delay between SATA0 and SATA
of 500ps.
I simplified the program as much as posible and this delay is alway
present.
The mesurment was made with the same cable lenght.

Same ideas?
Thansk
Marcelo





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Tue Feb 16, 2010 4:52 pm   

On 2/15/2010 10:08 PM, msegura wrote:

What are these two signals? Where do they connect to your FPGA?

Syms.

Tue Feb 16, 2010 7:30 pm   

On Feb 15, 2:08 pm, "msegura" <ms_...@usc.edu> wrote:

The lane-to-lane skew isn't zero and the maximum value is listed in
the device datasheet. For instance with Virtex-5 the GTP value is
855ps.

Ed McGettigan
--
Xilinx Inc.

Fri Feb 19, 2010 8:58 pm   

Ed,
So you told me that its no posible to sent two bits using diferent MGT with the same delay
But how work the comm systems that use several paralle channels
I'll check the datasheet for my virtex2p
Marcelo

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frmsrcurl: http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1

Sat Feb 20, 2010 5:06 am   

On Fri, 19 Feb 2010 13:58:25 -0600, Marcelo <user_at_compgroups.net/>
wrote:


Inter-lane skew is handled in the controller during training. Transmit
skew is not the only cause of skew, channel (cable or pcb) and
receivers also contribute to it too. It's much easier to manage it in
digital domain after data recovery than to try to make perfect
channels.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Sat Feb 20, 2010 6:21 pm   

On 2/19/2010 7:58 PM, Marcelo wrote:

http://en.wikipedia.org/wiki/XAUI

Mon Feb 22, 2010 3:03 am   

yes I understand but 500ps is to much for pcb delay, are 15cm
The idia is ti desing an ultra wideband transmiter using the MGT
I'm using BPKS modulation, so the delay between TX1(positive pulse) and TX2(negativo pulse), must be the same


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frmsrcurl: http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1

Mon Feb 22, 2010 7:00 am   

On Feb 19, 11:58 am, Marcelo <u...@compgroups.net/> wrote:

For interfaces that use multiple MGTs, such as PCIe and XAUI, the
protocol uses channel bonding that allows the receiver to align the
data correctly with multiple (1-40+) bits of skew. The are some
standards that want to skimp on the logic resources needed to
implement channel bonding and have a tighter requirement on the lane
skew, but the protocols that I am aware of still allow for about
1000pS of lane skew.

Expecting 0pS of lane skew is not realistic.

Ed McGettigan
--
Xilinx Inc.

Mon Feb 22, 2010 11:18 am   

On 2/22/2010 2:03 AM, marcelo wrote:

Do you remember this reply from a week ago?


"What are these two signals? Where do they connect to your FPGA?"


Why don't you answer it?

Symon.

Mon Feb 22, 2010 11:56 am   

On 2/22/2010 10:18 AM, Symon wrote:

Sorry, ignore that. I thought you were the OP. FWIW, the P and N signals
will be aligned to within a few ps. Different lanes will not be.

HTH,

Syms.

Mon Feb 22, 2010 6:45 pm   

Ok thanks all for your help
I will try using diferent DCM for each MGT
I hope that works


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frmsrcurl: http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1

Tue Feb 23, 2010 2:07 am   

On Feb 21, 6:03 pm, marcelo <u...@compgroups.net/> wrote:

500pS is 7.7cm assuming 65pS/cm in typical FR-4 material.

I'm not a RF DSP expert, but why do you need two separate transmitters
for this design? What component are the transmitters connected to in
the system?

Ed McGettigan
--
Xilinx Inc.

Tue Feb 23, 2010 3:02 am   

I need two transmiters, because I transmit BPSK pulse so positive and negative pulses
The time bettwen pulses is 150 ns, so if I change the polarity of MGT, the output capacitor of the bord charge and discharge so I can't see the pulse at the output
I don't know what hapen if I remove this capacitors
thanks

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frmsrcurl: http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1

Tue Feb 23, 2010 4:34 am   

On Feb 22, 6:02 pm, Marcelo Segura <u...@compgroups.net/> wrote:

I don't understand what you mean here, is there a diagram somewhere on
the web that illustrates what you are attempting to do?

Ed McGettigan
--
Xilinx Inc.