Nial Stewart
Guest
Fri Aug 05, 2011 3:43 pm
Quote:
The balance has stemmed from folks taking the Xilinx speed grades at face
value, and using what the synthesis tool says (using Xilinx's defaults)
at face value. Once the group learned that you have to force a bit of
margin into the process (and the group thinks that a design that fails to
synthesize once out of ten is a problem, as opposed to thinking that a
design that succeeds once out of twenty is 'shippable') then those
problems went away.
Tim, are talking about synthesis or the timing analysis after P&R?
Nial
Tim Wescott
Guest
Fri Aug 05, 2011 4:41 pm
On Fri, 05 Aug 2011 16:43:01 +0100, Nial Stewart wrote:
Quote:
The balance has stemmed from folks taking the Xilinx speed grades at
face value, and using what the synthesis tool says (using Xilinx's
defaults) at face value. Once the group learned that you have to force
a bit of margin into the process (and the group thinks that a design
that fails to synthesize once out of ten is a problem, as opposed to
thinking that a design that succeeds once out of twenty is 'shippable')
then those problems went away.
Tim, are talking about synthesis or the timing analysis after P&R?
Sorry -- muddled thinking working in concert with mostly being an
observer.
Timing analysis after P&R, yes.
--
www.wescottdesign.com
