George Fang
Guest
Tue Oct 28, 2003 10:56 pm
Hi everyone,
We have a circuit that latches data every 4 clock cycles. I used
"set_multicycle_path 4 -from FF1 -to FF2" to constrain the path. The
PrimeTime STA reported no setup timing violations but reported a large hold
timing violation. From the timing report we saw that the reference edge for
hold timing check is moved to clock edge 2 instead of clock edge 0 as stated
in the man page. Could someone firmiliar with Synopsys tools explain how to
use "set_multicycle_path" to move only the setup check reference edge and
leave the hold check reference edge at 0?
Thanks in advance for any info in this regard.
George
Ansgar Bambynek
Guest
Wed Oct 29, 2003 9:57 am
Hi George,
set_multicycle_path has a- setup and a -hold switch.
set_multicycle_path 4 -setup ...
set_multicycle_path 3 -hold
will do what you want.
In general the hold multiplier, i.e. the clock edge for which a hold time
check will be performed is changed by a multicylce path constraint to the
clock edge preceding the setup check.
So if you have a setup multiplier of N you have to use a hold multiplier of
N-1 to get the desired behaviour.
The sold docu and solvnet should give you a more dertailed explanation.
HTH
Ansgar
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"George Fang" <gfang10_at_cox.net> schrieb im Newsbeitrag
news:jEBnb.36181$Rd4.7951_at_fed1read07...
Quote:
Hi everyone,
We have a circuit that latches data every 4 clock cycles. I used
"set_multicycle_path 4 -from FF1 -to FF2" to constrain the path. The
PrimeTime STA reported no setup timing violations but reported a large
hold
timing violation. From the timing report we saw that the reference edge
for
hold timing check is moved to clock edge 2 instead of clock edge 0 as
stated
in the man page. Could someone firmiliar with Synopsys tools explain how
to
use "set_multicycle_path" to move only the setup check reference edge and
leave the hold check reference edge at 0?
Thanks in advance for any info in this regard.
George
