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elektroda.net NewsGroups Forum Index - Verilog Language - Question about 8'bx etc.

Robert Willy
Guest

Sat Mar 17, 2018 8:45 pm

Hi,
I am learning verilog and find an online discussion interesting:

https://stackoverflow.com/questions/5927615/what-is-the-difference-between-and-in-verilog

First of all, I find 8'bx is an interesting thing:

if (dataoutput[7:0] == 8'bx) begin

Is it an abbreviation of 8'bxxxxxxxx?

Then, it gave:

dataoutput = 52'bx

According to verilog grammar, it means 52-bit, value 'x'.
I don't think the OP meant that. Did he mean a value '52'?
Or, he meant anything else?

BTW, I simulate the above code in ModelSim, but it doesn't make me clear yet.

Thanks,

Amolak Singh
Guest

Mon Mar 19, 2018 6:45 am

On Sunday, March 18, 2018 at 12:47:40 AM UTC+5:30, Robert Willy wrote:
Quote:
Hi,
I am learning verilog and find an online discussion interesting:

https://stackoverflow.com/questions/5927615/what-is-the-difference-between-and-in-verilog

First of all, I find 8'bx is an interesting thing:

if (dataoutput[7:0] == 8'bx) begin

Is it an abbreviation of 8'bxxxxxxxx?

Then, it gave:

dataoutput = 52'bx

According to verilog grammar, it means 52-bit, value 'x'.
I don't think the OP meant that. Did he mean a value '52'?
Or, he meant anything else?

BTW, I simulate the above code in ModelSim, but it doesn't make me clear yet.

Thanks,

Yes 8'bx means extend Xs for all the 8 bits.
As for the question, it looks like the person is assigning a 52b wide bus, dataoutput with all Xs and then comparing which if statement gets executed when it wants to compare the lower 8 bits of the bus

elektroda.net NewsGroups Forum Index - Verilog Language - Question about 8'bx etc.