Carlos Barberis
Guest
Wed Sep 15, 2010 8:09 pm
Hi , I am pretty new to Verilog and was wondering if anyone could give a
hint for what should be a simple rutine
I need to accurately generate four pulses that have a variable pulse width
and variable timing between them. One of the pulses
will be a master pulse or the reference timing pulse all other pulses wll
follow this pulse by some time variable time delay
The whole sequence of pulses will repeat periodically at a rate of 30.0KHz
____|____________________|____ Pulse 1 Master sync
_______|____________________|_ Pulse 2
____________|_________________ Pulse 3
__________________|___________ Pulse 4
I would imagine that I would have to create one master counter or perhaps
four counters where three of them
are synchronous to the first and some form of parallel data load to enter
the delay values between the pulses and pulse width values
for all pulses. Any ideas or hints would be greatly apreciated. Thank you
Carlos Barberis
Guest
Wed Sep 15, 2010 10:17 pm
Actually, what I am trying to do is to generate these four pulses to drive a
power converter, I need synthesizable code, I believe the # operator is used
for test benching and not for what I am trying to do, I thank you for your
help.
"glen herrmannsfeldt" <gah_at_ugcs.caltech.edu> wrote in message
news:i6r925$17f$1_at_speranza.aioe.org...
Quote:
Carlos Barberis <carlos_at_bartek.com> wrote:
(snip)
I need to accurately generate four pulses that have a variable
pulse width and variable timing between them.
(snip)
I would imagine that I would have to create one master counter
or perhaps four counters where three of them are synchronous
to the first
(snip)
As you don't say why or how you are doing this, it is hard to say.
If you need something synthesizable, you will need counters
and such. If you only need to simulate, then you can use
the verilog delay (# operator) to generate various timing
related pulses.
So, yes, your hint is to look up the # operation in you book.
-- glen
glen herrmannsfeldt
Guest
Wed Sep 15, 2010 11:07 pm
Carlos Barberis <carlos_at_bartek.com> wrote:
(snip)
Quote:
I need to accurately generate four pulses that have a variable
pulse width and variable timing between them.
(snip)
Quote:
I would imagine that I would have to create one master counter
or perhaps four counters where three of them are synchronous
to the first
(snip)
As you don't say why or how you are doing this, it is hard to say.
If you need something synthesizable, you will need counters
and such. If you only need to simulate, then you can use
the verilog delay (# operator) to generate various timing
related pulses.
So, yes, your hint is to look up the # operation in you book.
-- glen
glen herrmannsfeldt
Guest
Thu Sep 16, 2010 12:33 am
Carlos Barberis <carlos_at_bartek.com> wrote:
Quote:
Actually, what I am trying to do is to generate these four pulses to drive a
power converter, I need synthesizable code, I believe the # operator is used
for test benching and not for what I am trying to do, I thank you for your
help.
Yes, your question sounded like it was for simulation, but I
wasn't so sure.
(snip)
Quote:
I need to accurately generate four pulses that have a variable
pulse width and variable timing between them.
(snip)
I would imagine that I would have to create one master counter
or perhaps four counters where three of them are synchronous
to the first
How fast, and how accurate, do the pulses and pulse positions
have to be?
How about one counter, comparators for the start and end
count, then a register to store the appropriate value.
As the start count it gets 1, at the end count 0, and
at all other counts the previous value. Register on
the same clock as the counter. Faster clock and more
bits on the comparators allows for finer positioning
of the pulse edges.
Pretty easy to implement in an FPGA.
-- glen
