gopal
Guest
Thu Apr 13, 2006 11:12 am
Hi All,
I had recently attended couple of interviews and had come across these
questions. What I had answered seems to be not convincing to the panel.
I would like to know, if any one of you have any additional information
in this regard.
More-Skew
More-Latency
=========================================================
Disadvantages: 1. More hold violations 1. More
prone to OCV
2. Might cause timing violations while
toplevel integration
3. More switching power
=========================================================
Less-Skew
Less-Latency
=========================================================
Disadvantages: 1. More IR Drop 1. No
disadvantages
Flops would be switching @ same time
=========================================================
Other questions are:
1. Is there any limit on skew number in a design?
- As per my knowledge one can have skew 5% of clock period. This
answer is not convincing. Any other thought?
2. Similarly on insertion delay also? Is there any hard bound limit for
this?
Can some one through light on this topic?
Regards,
Gopal.
SS
Guest
Thu Apr 27, 2006 1:39 pm
I know that skew is bad for domino circuits and they have to be
designed taking skew into consideration.
And they cause timing violations(both setup and hold -> loss of money).
Skew should be as minimal as possible.
http://www.deepchip.com/items/0409-01.html is an article which you
might find useful.
eda_cadence
Guest
Fri May 12, 2006 6:49 am
can u send the eact table framed in file format.
i cant clear understand the table of advan/disadvantage
