Post-synthèse simulation

Sun Jan 29, 2012 4:59 pm   

Hello,

I want to run a post-synthesis simulation. I don't find where to
choose the sources (Netlist post-synthesis) to launch the needed
simulation from ISE 13.3.

Does someone know how to do it ? I need some help.

Simulator: ModelSim SE-64 10.0d
Xilinx tools: 13.3

Molka
PhD student

Sun Jan 29, 2012 4:59 pm   

Why do you want to do this? I have never had a reason to do this and m
designs have all worked just fine. Just do a behavioural sim and ensur
your design passes timing and you will be ok.

Jon

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Mon Jan 30, 2012 5:03 am   

One scenario that comes to mind is to avoid annoying problems where the
behavioural models are broken. See this thread about the Xilinx FIFO core:

http://forums.xilinx.com/t5/Simulation-and-Verification/Spartan-6-FIFO-problem-in-13-1/td-p/154690

Joel

Mon Jan 30, 2012 7:37 pm   

On Jan 29, 9:36 am, "maxascent"
<maxascent_at_n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:

I would qualify that you should run full simulations on RTL, run STA
with complete and accurate timing constraints on the design, and then
run a subset of your simulation post-P&R. If you have any non-timing
issues PPR, then you might try a post-synthesis simulation to isolate
the problem to synthesis or P&R. One of the issues not caught by
behavioral simulation plus STA is the accuracy of false- and multi-
cycle-path constraints. If you use these in STA, they need to be
verified by PPR simulation.

Andy

Tue Jan 31, 2012 12:20 pm   

The correct workaround for this problem is to generate Structural FIF
models, and use them in your pre-synthesis simulations. AFAIK, all th
Behavioural FIFO models are broken.

I can think of other reasons to do post-PAR simulations, for instance i
you have a tricksy start-up sequence involving multiple clocks.


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Wed Feb 01, 2012 4:13 pm   

From within ISE13.3's Project Manager, having a VHDL project:
Select the "Design" tab
In the Hierarchy pane (upper area) select the top-level unit of you
design
In the Processes pane (lower area), expand "Synthesize - XST" an
double-click on "Generate Post Synthesis Simulation Model"
This generates a folder within your project named netgen/synthesis an
within this folder, there is a file named <top>_synthesis, where <top> i
the name of your project's top level VHDL file.
This file must be compiled with ModelSim, together with your testbench.
I'm not sure what is necessary to launch ModelSim directly from ISE
because I'm always using separate scripts for ModelSim.

regards
Guenter




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