leon
Guest
Wed Oct 12, 2011 9:50 pm
Hi,
I would like to have parameterized functions in packages. These
functions need to be used in different modules which will be
instantiated with different parameter sizes. System Verilog treats
parameters in packages as localparam and cannot be overriden. Is there
another mechanism to do this so the code is synthesizable.
Noel
Jonathan Bromley
Guest
Sat Oct 15, 2011 1:15 pm
On Wed, 12 Oct 2011 12:50:59 -0700 (PDT), leon wrote:
Quote:
I would like to have parameterized functions in packages. These
functions need to be used in different modules which will be
instantiated with different parameter sizes. System Verilog treats
parameters in packages as localparam and cannot be overriden. Is there
another mechanism to do this so the code is synthesizable.
Yes. Use a parameterized class, with static methods, as a
substitute for a package. (The class itself can go in a
package, of course.
You can then create a typedef for the class with any parameter
specialization you choose, and call the functions in it.
Here's a stupid example that may illustrate the idea.
class n_bit_printer (parameter N = 1);
static function void print(v: logic [N-1:0]);
$display("value = %0d'b%b", N, v);
endfunction
endclass
module test_with_16_bits;
logic [15:0] a;
typedef n_bit_printer #(16) printer16;
initial begin
printer16::print(a);
end
endmodule
--
Jonathan Bromley
Mark Curry
Guest
Mon Oct 17, 2011 4:19 pm
In article <be1j97tj5adko8amfhkjspa1g665lokioj_at_4ax.com>,
Jonathan Bromley <spam_at_oxfordbromley.plus.com> wrote:
Quote:
On Wed, 12 Oct 2011 12:50:59 -0700 (PDT), leon wrote:
I would like to have parameterized functions in packages. These
functions need to be used in different modules which will be
instantiated with different parameter sizes. System Verilog treats
parameters in packages as localparam and cannot be overriden. Is there
another mechanism to do this so the code is synthesizable.
Yes. Use a parameterized class, with static methods, as a
substitute for a package. (The class itself can go in a
package, of course.
You can then create a typedef for the class with any parameter
specialization you choose, and call the functions in it.
Here's a stupid example that may illustrate the idea.
class n_bit_printer (parameter N = 1);
static function void print(v: logic [N-1:0]);
$display("value = %0d'b%b", N, v);
endfunction
endclass
module test_with_16_bits;
logic [15:0] a;
typedef n_bit_printer #(16) printer16;
initial begin
printer16::print(a);
end
endmodule
That's how I do it too. Unfortunetly it fails on Leon's last requirement doesn't
it? It's not synthesizable. Unless there's a tool out there I'm unware of that'll
synthesize a primitive class like this.
Leon, for synthesis, I just don't use functions for things like this. I'd love
too, but can't for the reasons you've discovered. I usually end up making
a parameterized module instead of the function. Not as flexible, but get's the job done.
Hope this helps.
--Mark
