Calvin C
Guest
Tue Sep 14, 2010 9:58 pm
Hi all,
Are there any pros and cons in VHDL for placing noise filter on master
reset, i.e. inserting noise filter between ASIC/FPGA master reset
input and reset pins on internal FFs ?
Thanks,
Calvin
Andy
Guest
Wed Sep 15, 2010 12:03 am
I assume you mean a digital filter?
Generally speaking, you want as little logic between master reset and
the FPGA flops as possible. Inserting a filter would also assume that
you had a dependable clock source to run the filter (our master resets
are asynchronous because we need to control the state even with no
clock). We synchronize the trailing edge of reset to each destination
clock domain in order to avoid metastability problems, but it still
works without a clock to get the chip into reset (it just won't come
out of reset until you have a clock, which is not a bad thing.)
Andy
Calvin C
Guest
Wed Sep 15, 2010 12:20 am
Yes, I meant digital filter.
Normally, a master reset should be asynchronous asserted and
synchronous de-asserted, i.e. by clock edge as you mentioned.
Will we deviate from IEEE standards by placing digital filter on
master reset line ?
What could be the drawback for doing so ?
Thx,
Calvin
On Sep 14, 2:03 pm, Andy <jonesa...@comcast.net> wrote:
Quote:
I assume you mean a digital filter?
Generally speaking, you want as little logic between master reset and
the FPGA flops as possible. Inserting a filter would also assume that
you had a dependable clock source to run the filter (our master resets
are asynchronous because we need to control the state even with no
clock). We synchronize the trailing edge of reset to each destination
clock domain in order to avoid metastability problems, but it still
works without a clock to get the chip into reset (it just won't come
out of reset until you have a clock, which is not a bad thing.)
Andy
KJ
Guest
Wed Sep 15, 2010 2:31 am
On Sep 14, 5:20 pm, Calvin C <phuxuan...@gmail.com> wrote:
Quote:
Will we deviate from IEEE standards by placing digital filter on
master reset line ?
What IEEE standards are you referring to?
Quote:
What could be the drawback for doing so ?
You won't have found and fixed the cause of the noise on your master
reset, just attempted to cover it up. Probably will come back to
haunt you.
KJ
Calvin C
Guest
Wed Sep 15, 2010 3:46 pm
I'd rather say common standard practice, not IEEE standards, are to
avoid logic on master reset line.
Due to its nature, i.e. at much higher frequency, the clock line is
supposed to be more sensitive to noise than the reset line.
However, if digital filter were to be placed on the master reset line,
would that be enough to take care of noise concerns ?
CC
On Sep 14, 5:23 pm, KJ <kkjenni...@sbcglobal.net> wrote:
Quote:
On Sep 14, 5:20 pm, Calvin C <phuxuan...@gmail.com> wrote:
Will we deviate from IEEE standards by placing digital filter on
master reset line ?
What IEEE standards are you referring to?
What could be the drawback for doing so ?
You won't have found and fixed the cause of the noise on your master
reset, just attempted to cover it up. Probably will come back to
haunt you.
KJ
KJ
Guest
Wed Sep 15, 2010 7:49 pm
On Sep 15, 8:46 am, Calvin C <phuxuan...@gmail.com> wrote:
Quote:
Due to its nature, i.e. at much higher frequency, the clock line is
supposed to be more sensitive to noise than the reset line.
By that logic, you should be asking about noise filters on the clock,
not reset.
Quote:
However, if digital filter were to be placed on the master reset line,
would that be enough to take care of noise concerns ?
Sure...if your design has only input and that input is the master
reset.
But filtering also assumes that you have an understanding of the
nature of the noise you are filtering so that you can design a proper
filter...and for whatever reason, you are unable to eliminate the
noise source in the first place and can only apply filter band-aids.
KJ
