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Guest

Thu Nov 10, 2016 7:26 pm   



this is adopted code of the original code, where I simply replaced all "and" by "or"
Code:

---------------------------------------------------------
-- Author : http://www.teahlab.com/
--
-- Circuit: or Gate
--
-- Note   : This VHDL program is a structural description
--         of the interactive or Gate on teahlab.com.
--
--         If you are new to VHDL, then notice how the
--         program is designed: 1] first we declare the
--         ENTITY, which is where we define the inputs
--         and the outputs of the circuit. 2] Second
--         we present the ARCHITECTURE, which is where
--         we describe the behavior and function of
--         the circuit.
---------------------------------------------------------

--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;

--ENTITY DECLARATION: name, inputs, outputs
entity orGate is               
   port( A, B : in std_logic;
            F : out std_logic);
end orGate;

--FUNCTIONAL DESCRIPTION: how the or Gate works
architecture func of orGate is
begin
  F <= A or B;      
end func;
------------------------------------------------------END
------------------------------------------------------END


same in Testbench:
Code:

------------------------------------------------------------
-- Author  : http://www.teahlab.com/
--
-- Program : OR Gate Testbench
--
-- Note    : A testbench is a program that defines a set
--         of input signals to verity the operation of
--         a circuit: in this case, the or Gate.
--   
--         1] The testbench takes no inputs or returns
--         no outputs. As such the ENTITY declaration
--         is empty.
--
--         2] The circuit under verification, here the
--         or Gate, is imported into the testbench
--         ARCHITECTURE as a component.
------------------------------------------------------------

--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;

--ENTITY DECLARATION: no inputs, no outputs
entity orGate_tb is
end orGate_tb;

-- Describe how to test the or Gate
architecture tb1 of orGate_tb is
   --pass orGate entity to the testbench as component
   component orGate is   
   port( A, B : in std_logic;
            F : out std_logic);
   end component;
   
   signal  inA, inB, outF : std_logic;
begin
   --map the testbench signals to the ports of the orGate
   mapping: orGate port map(inA, inB, outF);

   process
      --variable to track errors
      variable errCnt : integer := 0;
   begin
      --TEST 1
      inA <= '0';
      inB <= '0';
      wait for 15 ns;
      assert(outF = '0')  report "Error 1"  severity error;
      if(outF /= '0') then
         errCnt := errCnt + 1;
      end if;

      --TEST 2
      inA <= '0';
      inB <= '1';
      wait for 15 ns;
      assert(outF = '0')  report "Error 2<---"  severity error;
      if(outF /= '0') then
         errCnt := errCnt + 1;
      end if;

      --TEST 3
      inA <= '1';
      inB <= '1';
      wait for 15 ns;
      assert(outF = '1')  report "Error 3"  severity error;
      if(outF /= '1') then
         errCnt := errCnt + 1;
      end if;

      -------------- SUMMARY -------------
      if(errCnt = 0) then
         assert false report "Good!"   severity note;
      else
         assert true report "Error!"   severity error;
      end if;

   end process;
end tb1;
--------------------------------------------
configuration cfg_tb1 of orGate_tb is
   for tb1
   end for;
end cfg_tb1;
---------------------------------------------------------END
---------------------------------------------------------END

in this I added a "1" to the "tb"

ghdl shows non error on the "and"-Simulation (also via gtkwave)
ghdl shows non error on ghdl -a or.vhdl
ghdl shows non error on ghdl -a or_tb.vhdl
ghdl shows non error on ghdl -e or_tb
but ghdl shows continuously errors on ghdl -r or_tb
"...(assertion error): Error 2<---"

I manually added the "<---" to the "Error 2"-mark to see if is THIS "Error2" or another compiler-error.

So, what is wrong in Test 2 of or_tb ?

Mike.

GaborSzakacs
Guest

Fri Nov 11, 2016 2:03 am   



mike.be_at_gmx.de wrote:
Quote:
this is adopted code of the original code, where I simply replaced all "and" by "or"
Code:

---------------------------------------------------------
-- Author : http://www.teahlab.com/
--
-- Circuit: or Gate
--
-- Note   : This VHDL program is a structural description
--         of the interactive or Gate on teahlab.com.
--
--         If you are new to VHDL, then notice how the
--         program is designed: 1] first we declare the
--         ENTITY, which is where we define the inputs
--         and the outputs of the circuit. 2] Second
--         we present the ARCHITECTURE, which is where
--         we describe the behavior and function of
--         the circuit.
---------------------------------------------------------

--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;

--ENTITY DECLARATION: name, inputs, outputs
entity orGate is               
port( A, B : in std_logic;
F : out std_logic);
end orGate;

--FUNCTIONAL DESCRIPTION: how the or Gate works
architecture func of orGate is
begin
F <= A or B;      
end func;
------------------------------------------------------END
------------------------------------------------------END


same in Testbench:
Code:

------------------------------------------------------------
-- Author  : http://www.teahlab.com/
--
-- Program : OR Gate Testbench
--
-- Note    : A testbench is a program that defines a set
--         of input signals to verity the operation of
--         a circuit: in this case, the or Gate.
--   
--         1] The testbench takes no inputs or returns
--         no outputs. As such the ENTITY declaration
--         is empty.
--
--         2] The circuit under verification, here the
--         or Gate, is imported into the testbench
--         ARCHITECTURE as a component.
------------------------------------------------------------

--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;

--ENTITY DECLARATION: no inputs, no outputs
entity orGate_tb is
end orGate_tb;

-- Describe how to test the or Gate
architecture tb1 of orGate_tb is
--pass orGate entity to the testbench as component
component orGate is   
port( A, B : in std_logic;
F : out std_logic);
end component;
   
signal  inA, inB, outF : std_logic;
begin
--map the testbench signals to the ports of the orGate
mapping: orGate port map(inA, inB, outF);

process
--variable to track errors
variable errCnt : integer := 0;
begin
--TEST 1
inA <= '0';
inB <= '0';
wait for 15 ns;
assert(outF = '0')  report "Error 1"  severity error;
if(outF /= '0') then
errCnt := errCnt + 1;
end if;

--TEST 2
inA <= '0';
inB <= '1';
wait for 15 ns;
assert(outF = '0')  report "Error 2<---"  severity error;
if(outF /= '0') then
errCnt := errCnt + 1;
end if;

--TEST 3
inA <= '1';
inB <= '1';
wait for 15 ns;
assert(outF = '1')  report "Error 3"  severity error;
if(outF /= '1') then
errCnt := errCnt + 1;
end if;

-------------- SUMMARY -------------
if(errCnt = 0) then
assert false report "Good!"   severity note;
else
assert true report "Error!"   severity error;
end if;

end process;
end tb1;
--------------------------------------------
configuration cfg_tb1 of orGate_tb is
for tb1
end for;
end cfg_tb1;
---------------------------------------------------------END
---------------------------------------------------------END

in this I added a "1" to the "tb"

ghdl shows non error on the "and"-Simulation (also via gtkwave)
ghdl shows non error on ghdl -a or.vhdl
ghdl shows non error on ghdl -a or_tb.vhdl
ghdl shows non error on ghdl -e or_tb
but ghdl shows continuously errors on ghdl -r or_tb
"...(assertion error): Error 2<---"

I manually added the "<---" to the "Error 2"-mark to see if is THIS "Error2" or another compiler-error.

So, what is wrong in Test 2 of or_tb ?

Mike.


Ummm... The "error" is that the assertion failed because you neglected
to change the expected value of the output of an OR gate ('1') when one
input is '1' and the other input '0'. This shows that assertions are
working and caught the error in your testbench expected output.

--
Gabor

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